accel/amdxdna: Check interrupt register before mailbox_rx_worker exits

There is a timeout failure been found during stress tests. If the firmware
generates a mailbox response right after driver clears the mailbox channel
interrupt register, the hardware will not generate an interrupt for the
response. This causes the unexpected mailbox command timeout.

To handle this failure, driver checks the interrupt register before
exiting mailbox_rx_worker(). If there is a new response, driver goes back
to process it.

Signed-off-by: Lizhi Hou <lizhi.hou@amd.com>
Reviewed-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250226161810.4188334-1-lizhi.hou@amd.com

diff --git a/drivers/accel/amdxdna/amdxdna_mailbox.c b/drivers/accel/amdxdna/amdxdna_mailbox.c
index aa07e67400efa65e2c0c60bd004bf32a79703c3c..da1ac89bb78f1f03dc5c76a2f81a41ee0656e7f1 100644 (file)
--- a/drivers/accel/amdxdna/amdxdna_mailbox.c
+++ b/drivers/accel/amdxdna/amdxdna_mailbox.c
@@ -349,8 +349,6 @@ static irqreturn_t mailbox_irq_handler(int irq, void *p)
        trace_mbox_irq_handle(MAILBOX_NAME, irq);
        /* Schedule a rx_work to call the callback functions */
        queue_work(mb_chann->work_q, &mb_chann->rx_work);
-       /* Clear IOHUB register */
-       mailbox_reg_write(mb_chann, mb_chann->iohub_int_addr, 0);
 
        return IRQ_HANDLED;
 }
@@ -367,6 +365,9 @@ static void mailbox_rx_worker(struct work_struct *rx_work)
                return;
        }
 
+again:
+       mailbox_reg_write(mb_chann, mb_chann->iohub_int_addr, 0);
+
        while (1) {
                /*
                 * If return is 0, keep consuming next message, until there is
@@ -380,10 +381,18 @@ static void mailbox_rx_worker(struct work_struct *rx_work)
                if (unlikely(ret)) {
                        MB_ERR(mb_chann, "Unexpected ret %d, disable irq", ret);
                        WRITE_ONCE(mb_chann->bad_state, true);
-                       disable_irq(mb_chann->msix_irq);
-                       break;
+                       return;
                }
        }
+
+       /*
+        * The hardware will not generate interrupt if firmware creates a new
+        * response right after driver clears interrupt register. Check
+        * the interrupt register to make sure there is not any new response
+        * before exiting.
+        */
+       if (mailbox_reg_read(mb_chann, mb_chann->iohub_int_addr))
+               goto again;
 }
 
 int xdna_mailbox_send_msg(struct mailbox_channel *mb_chann,