]> www.infradead.org Git - users/willy/pagecache.git/commitdiff
net: phy: dp83tg720: wake up PHYs in managed mode
authorOleksij Rempel <o.rempel@pengutronix.de>
Fri, 14 Jun 2024 09:45:15 +0000 (11:45 +0200)
committerJakub Kicinski <kuba@kernel.org>
Wed, 19 Jun 2024 00:51:45 +0000 (17:51 -0700)
In case this PHY is bootstrapped for managed mode, we need to manually
wake it. Otherwise no link will be detected.

Cc: stable@vger.kernel.org
Fixes: cb80ee2f9bee1 ("net: phy: Add support for the DP83TG720S Ethernet PHY")
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Link: https://lore.kernel.org/r/20240614094516.1481231-1-o.rempel@pengutronix.de
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
drivers/net/phy/dp83tg720.c

index 326c9770a6dccc3c06586d7a96a4ff68c6578405..1186dfc70fb3cbbaeb5a35fd4db161174dd54a64 100644 (file)
 #define DP83TG720S_PHY_RESET                   0x1f
 #define DP83TG720S_HW_RESET                    BIT(15)
 
+#define DP83TG720S_LPS_CFG3                    0x18c
+/* Power modes are documented as bit fields but used as values */
+/* Power Mode 0 is Normal mode */
+#define DP83TG720S_LPS_CFG3_PWR_MODE_0         BIT(0)
+
 #define DP83TG720S_RGMII_DELAY_CTRL            0x602
 /* In RGMII mode, Enable or disable the internal delay for RXD */
 #define DP83TG720S_RGMII_RX_CLK_SEL            BIT(1)
@@ -154,10 +159,17 @@ static int dp83tg720_config_init(struct phy_device *phydev)
         */
        usleep_range(1000, 2000);
 
-       if (phy_interface_is_rgmii(phydev))
-               return dp83tg720_config_rgmii_delay(phydev);
+       if (phy_interface_is_rgmii(phydev)) {
+               ret = dp83tg720_config_rgmii_delay(phydev);
+               if (ret)
+                       return ret;
+       }
 
-       return 0;
+       /* In case the PHY is bootstrapped in managed mode, we need to
+        * wake it.
+        */
+       return phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_LPS_CFG3,
+                            DP83TG720S_LPS_CFG3_PWR_MODE_0);
 }
 
 static struct phy_driver dp83tg720_driver[] = {