drm/i915: Parameterize PWRCTX_MAXCNT

Rather than having separate definitions for each engine, create a single
parameterized macro that takes the engine base offset.  This will also
ensure we get to the proper offset if we ever need to use these
registers on newer platforms (where the media engine offsets have
changed).

Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220111051600.3429104-3-matthew.d.roper@intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index 43093dd2d0c9eaf2bd9b32daf11f8bb466317447..68ad99ac83e5d3961546ae6112cc6806445d74be 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -442,10 +442,10 @@ static bool bxt_check_bios_rc6_setup(struct intel_rc6 *rc6)
                enable_rc6 = false;
        }
 
-       if (!((intel_uncore_read(uncore, PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1 &&
-             (intel_uncore_read(uncore, PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1 &&
-             (intel_uncore_read(uncore, PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1 &&
-             (intel_uncore_read(uncore, PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1)) {
+       if (!((intel_uncore_read(uncore, PWRCTX_MAXCNT(RENDER_RING_BASE)) & IDLE_TIME_MASK) > 1 &&
+             (intel_uncore_read(uncore, PWRCTX_MAXCNT(GEN6_BSD_RING_BASE)) & IDLE_TIME_MASK) > 1 &&
+             (intel_uncore_read(uncore, PWRCTX_MAXCNT(BLT_RING_BASE)) & IDLE_TIME_MASK) > 1 &&
+             (intel_uncore_read(uncore, PWRCTX_MAXCNT(VEBOX_RING_BASE)) & IDLE_TIME_MASK) > 1)) {
                drm_dbg(&i915->drm,
                        "Engine Idle wait time not set properly.\n");
                enable_rc6 = false;

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ff9b9a1db8acb9d3fb940e708f0a3a4bcf4f7137..bb3f843052a9cc452a3da78743ef46bba58e1677 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8954,11 +8954,7 @@ enum {
 #define           RC6_CTX_IN_DRAM                      (1 << 0)
 #define  RC6_CTX_BASE                          _MMIO(0xD48)
 #define    RC6_CTX_BASE_MASK                   0xFFFFFFF0
-#define  PWRCTX_MAXCNT_RCSUNIT                 _MMIO(0x2054)
-#define  PWRCTX_MAXCNT_VCSUNIT0                        _MMIO(0x12054)
-#define  PWRCTX_MAXCNT_BCSUNIT                 _MMIO(0x22054)
-#define  PWRCTX_MAXCNT_VECSUNIT                        _MMIO(0x1A054)
-#define  PWRCTX_MAXCNT_VCSUNIT1                        _MMIO(0x1C054)
+#define  PWRCTX_MAXCNT(base)                   _MMIO((base) + 0x54)
 #define    IDLE_TIME_MASK                      0xFFFFF
 #define  FORCEWAKE                             _MMIO(0xA18C)
 #define  FORCEWAKE_VLV                         _MMIO(0x1300b0)