The new member num_ufs can be used by the PF driver to request a
number of UFs FW shall support.
0: use default value stored on card
1: PF (UF 0) only
...
33: fully virtualized
>33: capped by FW to 33 i.e. fully virtualized
-1: alternative PF only config not for official use
Orabug:
24424521
Reviewed-by: Knut Omang <knut.omang@oracle.com>
Signed-off-by: Knut Omang <knut.omang@oracle.com>
* Update when new operations are added or otherwise
* backward compatible changes are made
*/
-#define EPSC_MINOR_VERSION 8
+#define EPSC_MINOR_VERSION 9
/*
* Macros for EPSC API #if checking in code
u64 vlink_connect:1;
/** Setup CMPL spin set mode to be fast - default is safe (PF only). */
u64 fast_spin:1;
+ /** Number of UFs (PF+VFs) to configure HW for
+ * 0 means to use default stored in HW (PF only)
+ * Though this is a signed value (values < 0 are used for special settings
+ * not available in official FW) the created bitfield is unsigned. */
+ u64 num_ufs:16;
/** Padded field. */
- u64 noname:55;
+ u64 noname:39;
} PSIF_PACKED_ALIGNED; /* struct psif_epsc_csr_config [48 byte] */
/* This is the portion of the descriptor which is updated by software. */
/** MMU context for mailbox. */
struct psif_mmu_cntx mmu_cntx;
/** Padded field. */
- u64 noname:55;
+ u64 noname:39;
+ /** Number of UFs (PF+VFs) to configure HW for
+ * 0 means to use default stored in HW (PF only)
+ * Though this is a signed value (values < 0 are used for special settings
+ * not available in official FW) the created bitfield is unsigned. */
+ u64 num_ufs:16;
/** Setup CMPL spin set mode to be fast - default is safe (PF only). */
u64 fast_spin:1;
/** Connect all vlinks to external port (PF only). */