clk: renesas: rcar-gen4: Remove unused variable PLL2 clock type

The variable PLL2 clock type was superseded by the more generic
variable fractional 8.25 PLL clock type, and its sole user was converted.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/8e5564958002351f29435f63de1304fb3b51a725.1721648548.git.geert+renesas@glider.be

diff --git a/drivers/clk/renesas/rcar-gen4-cpg.c b/drivers/clk/renesas/rcar-gen4-cpg.c
index d3db602d7c5ec6171de7526d2fafd8e380a2b728..2a0f520d56b5aa9639426f1975aec919cca0529b 100644 (file)
--- a/drivers/clk/renesas/rcar-gen4-cpg.c
+++ b/drivers/clk/renesas/rcar-gen4-cpg.c
@@ -440,15 +440,6 @@ struct clk * __init rcar_gen4_cpg_clk_register(struct device *dev,
                div = cpg_pll_config->pll1_div;
                break;
 
-       case CLK_TYPE_GEN4_PLL2_VAR:
-               /*
-                * PLL2 is implemented as a custom clock, to change the
-                * multiplier when cpufreq changes between normal and boost
-                * modes.
-                */
-               return cpg_pll_clk_register(core->name, __clk_get_name(parent),
-                                           base, 2, &cpg_pll_v8_25_clk_ops);
-
        case CLK_TYPE_GEN4_PLL2:
                mult = cpg_pll_config->pll2_mult;
                div = cpg_pll_config->pll2_div;

diff --git a/drivers/clk/renesas/rcar-gen4-cpg.h b/drivers/clk/renesas/rcar-gen4-cpg.h
index 80a455e62cc1321e2f51d7c36d0fe3a1772746c2..2dadacacf3f911e226899f85ae3717b2b319eba3 100644 (file)
--- a/drivers/clk/renesas/rcar-gen4-cpg.h
+++ b/drivers/clk/renesas/rcar-gen4-cpg.h
@@ -13,7 +13,6 @@ enum rcar_gen4_clk_types {
        CLK_TYPE_GEN4_MAIN = CLK_TYPE_CUSTOM,
        CLK_TYPE_GEN4_PLL1,
        CLK_TYPE_GEN4_PLL2,
-       CLK_TYPE_GEN4_PLL2_VAR,
        CLK_TYPE_GEN4_PLL2X_3X, /* r8a779a0 only */
        CLK_TYPE_GEN4_PLL3,
        CLK_TYPE_GEN4_PLL4,