drm/amd/display: Add read backlight interface

[Why & How]
Add read backlight interface to get ABM data.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index 0257a900fe2bb779cd1d351e66e8dffa0079fe6d..f42a17d765e375f0ceb3609fe695e1dfdaa84a03 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -708,3 +708,4 @@ void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream)
                        "\tlink: %d\n",
                        stream->link->link_index);
 }
+

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
index a44effcda49f6985b1114a66903bcf564e86f608..e84d216058543348996b1dadeda28565f74db120 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
@@ -46,6 +46,8 @@
        SR(BL1_PWM_USER_LEVEL), \
        SR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES), \
        SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \
+       SR(DC_ABM1_ACE_OFFSET_SLOPE_0), \
+       SR(DC_ABM1_ACE_THRES_12), \
        SR(BIOS_SCRATCH_2)
 
 #define ABM_DCN10_REG_LIST(id)\
@@ -60,6 +62,8 @@
        SRI(BL1_PWM_USER_LEVEL, ABM, id), \
        SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
        SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
+       SRI(DC_ABM1_ACE_OFFSET_SLOPE_0, ABM, id), \
+       SRI(DC_ABM1_ACE_THRES_12, ABM, id), \
        NBIO_SR(BIOS_SCRATCH_2)
 
 #define ABM_DCN20_REG_LIST() \
@@ -74,10 +78,12 @@
        SR(BL1_PWM_USER_LEVEL), \
        SR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES), \
        SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \
+       SR(DC_ABM1_ACE_OFFSET_SLOPE_0), \
+       SR(DC_ABM1_ACE_THRES_12), \
        NBIO_SR(BIOS_SCRATCH_2)
 
 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
-#define ABM_DCN301_REG_LIST(id)\
+#define ABM_DCN30_REG_LIST(id)\
        ABM_COMMON_REG_LIST_DCE_BASE(), \
        SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
        SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \
@@ -89,6 +95,8 @@
        SRI(BL1_PWM_USER_LEVEL, ABM, id), \
        SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
        SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
+       SRI(DC_ABM1_ACE_OFFSET_SLOPE_0, ABM, id), \
+       SRI(DC_ABM1_ACE_THRES_12, ABM, id), \
        NBIO_SR(BIOS_SCRATCH_2)
 #endif
 
@@ -208,6 +216,8 @@ struct dce_abm_registers {
        uint32_t BL1_PWM_USER_LEVEL;
        uint32_t DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES;
        uint32_t DC_ABM1_HGLS_REG_READ_PROGRESS;
+       uint32_t DC_ABM1_ACE_OFFSET_SLOPE_0;
+       uint32_t DC_ABM1_ACE_THRES_12;
        uint32_t MASTER_COMM_CNTL_REG;
        uint32_t MASTER_COMM_CMD_REG;
        uint32_t MASTER_COMM_DATA_REG1;

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c b/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c
index 43781e77be431e08dc86df06ffbee0e120fbff17..a6d73d30837ca2d121d2817422b81aef622e0a86 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c
@@ -46,13 +46,14 @@
 #define FN(reg_name, field_name) \
        dce_panel_cntl->shift->field_name, dce_panel_cntl->mask->field_name
 
-static unsigned int calculate_16_bit_backlight_from_pwm(struct dce_panel_cntl *dce_panel_cntl)
+static unsigned int dce_get_16_bit_backlight_from_pwm(struct panel_cntl *panel_cntl)
 {
        uint64_t current_backlight;
        uint32_t round_result;
        uint32_t pwm_period_cntl, bl_period, bl_int_count;
        uint32_t bl_pwm_cntl, bl_pwm, fractional_duty_cycle_en;
        uint32_t bl_period_mask, bl_pwm_mask;
+       struct dce_panel_cntl *dce_panel_cntl = TO_DCE_PANEL_CNTL(panel_cntl);
 
        pwm_period_cntl = REG_READ(BL_PWM_PERIOD_CNTL);
        REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, &bl_period);
@@ -150,7 +151,7 @@ static uint32_t dce_panel_cntl_hw_init(struct panel_cntl *panel_cntl)
        REG_UPDATE(BL_PWM_GRP1_REG_LOCK,
                        BL_PWM_GRP1_REG_LOCK, 0);
 
-       current_backlight = calculate_16_bit_backlight_from_pwm(dce_panel_cntl);
+       current_backlight = dce_get_16_bit_backlight_from_pwm(panel_cntl);
 
        return current_backlight;
 }
@@ -273,6 +274,7 @@ static const struct panel_cntl_funcs dce_link_panel_cntl_funcs = {
        .is_panel_powered_on = dce_is_panel_powered_on,
        .store_backlight_level = dce_store_backlight_level,
        .driver_set_backlight = dce_driver_set_backlight,
+       .get_current_backlight = dce_get_16_bit_backlight_from_pwm,
 };
 
 void dce_panel_cntl_construct(

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index aa3ea6c79c2788f8af50ca8ce708c9fe171ef918..3b4c356c5ba6a3347d2fd0ffa7bdf44392a75809 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -340,7 +340,7 @@ static const struct dce110_clk_src_mask cs_mask = {
 
 #define abm_regs(id)\
 [id] = {\
-               ABM_DCN301_REG_LIST(id)\
+               ABM_DCN30_REG_LIST(id)\
 }
 
 static const struct dce_abm_registers abm_regs[] = {

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/panel_cntl.h b/drivers/gpu/drm/amd/display/dc/inc/hw/panel_cntl.h
index f9ab5abb64623fe07ceab8db676a539baef747dd..48eac622c6a0f67185c43c462299269c6f4e6015 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/panel_cntl.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/panel_cntl.h
@@ -49,6 +49,7 @@ struct panel_cntl_funcs {
        void (*store_backlight_level)(struct panel_cntl *panel_cntl);
        void (*driver_set_backlight)(struct panel_cntl *panel_cntl,
                        uint32_t backlight_pwm_u16_16);
+       uint32_t (*get_current_backlight)(struct panel_cntl *panel_cntl);
 };
 
 struct panel_cntl_init_data {