perf/x86/intel/pt: Bypass PT vs. LBR exclusivity if the core supports it

Not all cores prevent using Intel PT and LBRs simultaneously, although
most of them still do as of today. This patch adds an opt-in flag for
such cores to disable mutual exclusivity between PT and LBR; also flip
it on for Goldmont.

Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Cc: vince@deater.net
Link: http://lkml.kernel.org/r/1461857746-31346-4-git-send-email-alexander.shishkin@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>

diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index 41d93d0e972b32d6c3b4d5594cb9ee68bd307e0b..5e5e76a52f58cd60678ceb3401cbaa6a32378ede 100644 (file)
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -360,6 +360,9 @@ int x86_add_exclusive(unsigned int what)
 {
        int i;
 
+       if (x86_pmu.lbr_pt_coexist)
+               return 0;
+
        if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) {
                mutex_lock(&pmc_reserve_mutex);
                for (i = 0; i < ARRAY_SIZE(x86_pmu.lbr_exclusive); i++) {
@@ -380,6 +383,9 @@ fail_unlock:
 
 void x86_del_exclusive(unsigned int what)
 {
+       if (x86_pmu.lbr_pt_coexist)
+               return;
+
        atomic_dec(&x86_pmu.lbr_exclusive[what]);
        atomic_dec(&active_events);
 }

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 90ba3ae3074eead402d283bc1b01daabd82e9aa2..cd319400dc10605653b468a205591e60c5e9bde0 100644 (file)
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -3609,6 +3609,7 @@ __init int intel_pmu_init(void)
                 */
                x86_pmu.pebs_aliases = NULL;
                x86_pmu.pebs_prec_dist = true;
+               x86_pmu.lbr_pt_coexist = true;
                x86_pmu.flags |= PMU_FL_HAS_RSP_1;
                pr_cont("Goldmont events, ");
                break;

diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index 7d62a02f49a4120ffd0992711e7c96081acfaf25..8bd764df815d36287ca4b29effb969ede50735a6 100644 (file)
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -601,6 +601,7 @@ struct x86_pmu {
        u64             lbr_sel_mask;              /* LBR_SELECT valid bits */
        const int       *lbr_sel_map;              /* lbr_select mappings */
        bool            lbr_double_abort;          /* duplicated lbr aborts */
+       bool            lbr_pt_coexist;            /* LBR may coexist with PT */
 
        /*
         * Intel PT/LBR/BTS are exclusive