drm/i915: Extract intel_pipe_crc_regs.h

The CRC registers are a pretty self contained bunch.
Extract them to a separate header to declutter i915_reg.h.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240531115342.2763-2-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 1674570dff1e7c330dd5a9588ee34864b6c35294..9c12cc0f2ed0149f9d6fa6664d5027c846f662b4 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -18,6 +18,7 @@
 #include "intel_fifo_underrun.h"
 #include "intel_gmbus.h"
 #include "intel_hotplug_irq.h"
+#include "intel_pipe_crc_regs.h"
 #include "intel_pmdemand.h"
 #include "intel_psr.h"
 #include "intel_psr_regs.h"

diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc.c b/drivers/gpu/drm/i915/display/intel_pipe_crc.c
index b3dcfee6ec0e81946bdfe39c65c6f9d0b5c22975..82ceede0b2b1618531b166c11f12f79d5534a096 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_pipe_crc.c
+++ b/drivers/gpu/drm/i915/display/intel_pipe_crc.c
@@ -34,6 +34,7 @@
 #include "intel_de.h"
 #include "intel_display_types.h"
 #include "intel_pipe_crc.h"
+#include "intel_pipe_crc_regs.h"
 
 static const char * const pipe_crc_sources[] = {
        [INTEL_PIPE_CRC_SOURCE_NONE] = "none",

diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h b/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h
new file mode 100644 (file)
index 0000000..e684bc9
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h
@@ -0,0 +1,92 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2024 Intel Corporation
+ */
+
+#ifndef __INTEL_PIPE_CRC_REGS_H__
+#define __INTEL_PIPE_CRC_REGS_H__
+
+#include "intel_display_reg_defs.h"
+
+/* Pipe A CRC regs */
+#define _PIPE_CRC_CTL_A                        0x60050
+#define   PIPE_CRC_ENABLE              REG_BIT(31)
+/* skl+ source selection */
+#define   PIPE_CRC_SOURCE_MASK_SKL     REG_GENMASK(30, 28)
+#define   PIPE_CRC_SOURCE_PLANE_1_SKL  REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 0)
+#define   PIPE_CRC_SOURCE_PLANE_2_SKL  REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 2)
+#define   PIPE_CRC_SOURCE_DMUX_SKL     REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 4)
+#define   PIPE_CRC_SOURCE_PLANE_3_SKL  REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 6)
+#define   PIPE_CRC_SOURCE_PLANE_4_SKL  REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 7)
+#define   PIPE_CRC_SOURCE_PLANE_5_SKL  REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 5)
+#define   PIPE_CRC_SOURCE_PLANE_6_SKL  REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 3)
+#define   PIPE_CRC_SOURCE_PLANE_7_SKL  REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 1)
+/* ivb+ source selection */
+#define   PIPE_CRC_SOURCE_MASK_IVB     REG_GENMASK(30, 29)
+#define   PIPE_CRC_SOURCE_PRIMARY_IVB  REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 0)
+#define   PIPE_CRC_SOURCE_SPRITE_IVB   REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 1)
+#define   PIPE_CRC_SOURCE_PF_IVB       REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 2)
+/* ilk+ source selection */
+#define   PIPE_CRC_SOURCE_MASK_ILK     REG_GENMASK(30, 28)
+#define   PIPE_CRC_SOURCE_PRIMARY_ILK  REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 0)
+#define   PIPE_CRC_SOURCE_SPRITE_ILK   REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 1)
+#define   PIPE_CRC_SOURCE_PIPE_ILK     REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 2)
+/* embedded DP port on the north display block */
+#define   PIPE_CRC_SOURCE_PORT_A_ILK   REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 4)
+#define   PIPE_CRC_SOURCE_FDI_ILK      REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 5)
+/* vlv source selection */
+#define   PIPE_CRC_SOURCE_MASK_VLV     REG_GENMASK(30, 27)
+#define   PIPE_CRC_SOURCE_PIPE_VLV     REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 0)
+#define   PIPE_CRC_SOURCE_HDMIB_VLV    REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 1)
+#define   PIPE_CRC_SOURCE_HDMIC_VLV    REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 2)
+/* with DP port the pipe source is invalid */
+#define   PIPE_CRC_SOURCE_DP_D_VLV     REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 3)
+#define   PIPE_CRC_SOURCE_DP_B_VLV     REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 6)
+#define   PIPE_CRC_SOURCE_DP_C_VLV     REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 7)
+/* gen3+ source selection */
+#define   PIPE_CRC_SOURCE_MASK_I9XX    REG_GENMASK(30, 28)
+#define   PIPE_CRC_SOURCE_PIPE_I9XX    REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 0)
+#define   PIPE_CRC_SOURCE_SDVOB_I9XX   REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 1)
+#define   PIPE_CRC_SOURCE_SDVOC_I9XX   REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 2)
+/* with DP/TV port the pipe source is invalid */
+#define   PIPE_CRC_SOURCE_DP_D_G4X     REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 3)
+#define   PIPE_CRC_SOURCE_TV_PRE       REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 4)
+#define   PIPE_CRC_SOURCE_TV_POST      REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 5)
+#define   PIPE_CRC_SOURCE_DP_B_G4X     REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 6)
+#define   PIPE_CRC_SOURCE_DP_C_G4X     REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 7)
+/* gen2 doesn't have source selection bits */
+#define   PIPE_CRC_INCLUDE_BORDER_I8XX REG_BIT(30)
+
+#define _PIPE_CRC_RES_1_A_IVB          0x60064
+#define _PIPE_CRC_RES_2_A_IVB          0x60068
+#define _PIPE_CRC_RES_3_A_IVB          0x6006c
+#define _PIPE_CRC_RES_4_A_IVB          0x60070
+#define _PIPE_CRC_RES_5_A_IVB          0x60074
+
+#define _PIPE_CRC_RES_RED_A            0x60060
+#define _PIPE_CRC_RES_GREEN_A          0x60064
+#define _PIPE_CRC_RES_BLUE_A           0x60068
+#define _PIPE_CRC_RES_RES1_A_I915      0x6006c
+#define _PIPE_CRC_RES_RES2_A_G4X       0x60080
+
+/* Pipe B CRC regs */
+#define _PIPE_CRC_RES_1_B_IVB          0x61064
+#define _PIPE_CRC_RES_2_B_IVB          0x61068
+#define _PIPE_CRC_RES_3_B_IVB          0x6106c
+#define _PIPE_CRC_RES_4_B_IVB          0x61070
+#define _PIPE_CRC_RES_5_B_IVB          0x61074
+
+#define PIPE_CRC_CTL(dev_priv, pipe)           _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_CTL_A)
+#define PIPE_CRC_RES_1_IVB(dev_priv, pipe)     _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_1_A_IVB)
+#define PIPE_CRC_RES_2_IVB(dev_priv, pipe)     _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_2_A_IVB)
+#define PIPE_CRC_RES_3_IVB(dev_priv, pipe)     _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_3_A_IVB)
+#define PIPE_CRC_RES_4_IVB(dev_priv, pipe)     _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_4_A_IVB)
+#define PIPE_CRC_RES_5_IVB(dev_priv, pipe)     _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_5_A_IVB)
+
+#define PIPE_CRC_RES_RED(dev_priv, pipe)               _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RED_A)
+#define PIPE_CRC_RES_GREEN(dev_priv, pipe)     _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_GREEN_A)
+#define PIPE_CRC_RES_BLUE(dev_priv, pipe)              _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_BLUE_A)
+#define PIPE_CRC_RES_RES1_I915(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES1_A_I915)
+#define PIPE_CRC_RES_RES2_G4X(dev_priv, pipe)  _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES2_A_G4X)
+
+#endif /* __INTEL_PIPE_CRC_REGS_H__ */

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6877e2f0fbc3820124b8e41b413c9d1936823753..0569a23b83b2a115dd7b05ac6623895a6d649d94 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1069,87 +1069,6 @@
  * Display engine regs
  */
 
-/* Pipe A CRC regs */
-#define _PIPE_CRC_CTL_A                        0x60050
-#define   PIPE_CRC_ENABLE              REG_BIT(31)
-/* skl+ source selection */
-#define   PIPE_CRC_SOURCE_MASK_SKL     REG_GENMASK(30, 28)
-#define   PIPE_CRC_SOURCE_PLANE_1_SKL  REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 0)
-#define   PIPE_CRC_SOURCE_PLANE_2_SKL  REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 2)
-#define   PIPE_CRC_SOURCE_DMUX_SKL     REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 4)
-#define   PIPE_CRC_SOURCE_PLANE_3_SKL  REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 6)
-#define   PIPE_CRC_SOURCE_PLANE_4_SKL  REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 7)
-#define   PIPE_CRC_SOURCE_PLANE_5_SKL  REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 5)
-#define   PIPE_CRC_SOURCE_PLANE_6_SKL  REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 3)
-#define   PIPE_CRC_SOURCE_PLANE_7_SKL  REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 1)
-/* ivb+ source selection */
-#define   PIPE_CRC_SOURCE_MASK_IVB     REG_GENMASK(30, 29)
-#define   PIPE_CRC_SOURCE_PRIMARY_IVB  REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 0)
-#define   PIPE_CRC_SOURCE_SPRITE_IVB   REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 1)
-#define   PIPE_CRC_SOURCE_PF_IVB       REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 2)
-/* ilk+ source selection */
-#define   PIPE_CRC_SOURCE_MASK_ILK     REG_GENMASK(30, 28)
-#define   PIPE_CRC_SOURCE_PRIMARY_ILK  REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 0)
-#define   PIPE_CRC_SOURCE_SPRITE_ILK   REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 1)
-#define   PIPE_CRC_SOURCE_PIPE_ILK     REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 2)
-/* embedded DP port on the north display block */
-#define   PIPE_CRC_SOURCE_PORT_A_ILK   REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 4)
-#define   PIPE_CRC_SOURCE_FDI_ILK      REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 5)
-/* vlv source selection */
-#define   PIPE_CRC_SOURCE_MASK_VLV     REG_GENMASK(30, 27)
-#define   PIPE_CRC_SOURCE_PIPE_VLV     REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 0)
-#define   PIPE_CRC_SOURCE_HDMIB_VLV    REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 1)
-#define   PIPE_CRC_SOURCE_HDMIC_VLV    REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 2)
-/* with DP port the pipe source is invalid */
-#define   PIPE_CRC_SOURCE_DP_D_VLV     REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 3)
-#define   PIPE_CRC_SOURCE_DP_B_VLV     REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 6)
-#define   PIPE_CRC_SOURCE_DP_C_VLV     REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 7)
-/* gen3+ source selection */
-#define   PIPE_CRC_SOURCE_MASK_I9XX    REG_GENMASK(30, 28)
-#define   PIPE_CRC_SOURCE_PIPE_I9XX    REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 0)
-#define   PIPE_CRC_SOURCE_SDVOB_I9XX   REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 1)
-#define   PIPE_CRC_SOURCE_SDVOC_I9XX   REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 2)
-/* with DP/TV port the pipe source is invalid */
-#define   PIPE_CRC_SOURCE_DP_D_G4X     REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 3)
-#define   PIPE_CRC_SOURCE_TV_PRE       REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 4)
-#define   PIPE_CRC_SOURCE_TV_POST      REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 5)
-#define   PIPE_CRC_SOURCE_DP_B_G4X     REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 6)
-#define   PIPE_CRC_SOURCE_DP_C_G4X     REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 7)
-/* gen2 doesn't have source selection bits */
-#define   PIPE_CRC_INCLUDE_BORDER_I8XX REG_BIT(30)
-
-#define _PIPE_CRC_RES_1_A_IVB          0x60064
-#define _PIPE_CRC_RES_2_A_IVB          0x60068
-#define _PIPE_CRC_RES_3_A_IVB          0x6006c
-#define _PIPE_CRC_RES_4_A_IVB          0x60070
-#define _PIPE_CRC_RES_5_A_IVB          0x60074
-
-#define _PIPE_CRC_RES_RED_A            0x60060
-#define _PIPE_CRC_RES_GREEN_A          0x60064
-#define _PIPE_CRC_RES_BLUE_A           0x60068
-#define _PIPE_CRC_RES_RES1_A_I915      0x6006c
-#define _PIPE_CRC_RES_RES2_A_G4X       0x60080
-
-/* Pipe B CRC regs */
-#define _PIPE_CRC_RES_1_B_IVB          0x61064
-#define _PIPE_CRC_RES_2_B_IVB          0x61068
-#define _PIPE_CRC_RES_3_B_IVB          0x6106c
-#define _PIPE_CRC_RES_4_B_IVB          0x61070
-#define _PIPE_CRC_RES_5_B_IVB          0x61074
-
-#define PIPE_CRC_CTL(dev_priv, pipe)           _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_CTL_A)
-#define PIPE_CRC_RES_1_IVB(dev_priv, pipe)     _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_1_A_IVB)
-#define PIPE_CRC_RES_2_IVB(dev_priv, pipe)     _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_2_A_IVB)
-#define PIPE_CRC_RES_3_IVB(dev_priv, pipe)     _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_3_A_IVB)
-#define PIPE_CRC_RES_4_IVB(dev_priv, pipe)     _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_4_A_IVB)
-#define PIPE_CRC_RES_5_IVB(dev_priv, pipe)     _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_5_A_IVB)
-
-#define PIPE_CRC_RES_RED(dev_priv, pipe)               _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RED_A)
-#define PIPE_CRC_RES_GREEN(dev_priv, pipe)     _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_GREEN_A)
-#define PIPE_CRC_RES_BLUE(dev_priv, pipe)              _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_BLUE_A)
-#define PIPE_CRC_RES_RES1_I915(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES1_A_I915)
-#define PIPE_CRC_RES_RES2_G4X(dev_priv, pipe)  _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES2_A_G4X)
-
 /* Pipe/transcoder A timing regs */
 #define _TRANS_HTOTAL_A                0x60000
 #define   HTOTAL_MASK                  REG_GENMASK(31, 16)