serdes_phy_addr = intel_priv->mdio_adhoc_addr;
 
        /* assert clk_req */
-       data = mdiobus_read(priv->mii, serdes_phy_addr,
-                           SERDES_GCR0);
-
+       data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
        data |= SERDES_PLL_CLK;
-
-       mdiobus_write(priv->mii, serdes_phy_addr,
-                     SERDES_GCR0, data);
+       mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
 
        /* check for clk_ack assertion */
        data = serdes_status_poll(priv, serdes_phy_addr,
        }
 
        /* assert lane reset */
-       data = mdiobus_read(priv->mii, serdes_phy_addr,
-                           SERDES_GCR0);
-
+       data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
        data |= SERDES_RST;
-
-       mdiobus_write(priv->mii, serdes_phy_addr,
-                     SERDES_GCR0, data);
+       mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
 
        /* check for assert lane reset reflection */
        data = serdes_status_poll(priv, serdes_phy_addr,
        }
 
        /*  move power state to P0 */
-       data = mdiobus_read(priv->mii, serdes_phy_addr,
-                           SERDES_GCR0);
+       data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
 
        data &= ~SERDES_PWR_ST_MASK;
        data |= SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT;
 
-       mdiobus_write(priv->mii, serdes_phy_addr,
-                     SERDES_GCR0, data);
+       mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
 
        /* Check for P0 state */
        data = serdes_status_poll(priv, serdes_phy_addr,
        serdes_phy_addr = intel_priv->mdio_adhoc_addr;
 
        /*  move power state to P3 */
-       data = mdiobus_read(priv->mii, serdes_phy_addr,
-                           SERDES_GCR0);
+       data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
 
        data &= ~SERDES_PWR_ST_MASK;
        data |= SERDES_PWR_ST_P3 << SERDES_PWR_ST_SHIFT;
 
-       mdiobus_write(priv->mii, serdes_phy_addr,
-                     SERDES_GCR0, data);
+       mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
 
        /* Check for P3 state */
        data = serdes_status_poll(priv, serdes_phy_addr,
        }
 
        /* de-assert clk_req */
-       data = mdiobus_read(priv->mii, serdes_phy_addr,
-                           SERDES_GCR0);
-
+       data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
        data &= ~SERDES_PLL_CLK;
-
-       mdiobus_write(priv->mii, serdes_phy_addr,
-                     SERDES_GCR0, data);
+       mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
 
        /* check for clk_ack de-assert */
        data = serdes_status_poll(priv, serdes_phy_addr,
        }
 
        /* de-assert lane reset */
-       data = mdiobus_read(priv->mii, serdes_phy_addr,
-                           SERDES_GCR0);
-
+       data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
        data &= ~SERDES_RST;
-
-       mdiobus_write(priv->mii, serdes_phy_addr,
-                     SERDES_GCR0, data);
+       mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
 
        /* check for de-assert lane reset reflection */
        data = serdes_status_poll(priv, serdes_phy_addr,
        return ehl_common_data(pdev, plat);
 }
 
-static struct stmmac_pci_info ehl_sgmii1g_pci_info = {
+static struct stmmac_pci_info ehl_sgmii1g_info = {
        .setup = ehl_sgmii_data,
 };
 
        return ehl_common_data(pdev, plat);
 }
 
-static struct stmmac_pci_info ehl_rgmii1g_pci_info = {
+static struct stmmac_pci_info ehl_rgmii1g_info = {
        .setup = ehl_rgmii_data,
 };
 
        return ehl_pse0_common_data(pdev, plat);
 }
 
-static struct stmmac_pci_info ehl_pse0_rgmii1g_pci_info = {
+static struct stmmac_pci_info ehl_pse0_rgmii1g_info = {
        .setup = ehl_pse0_rgmii1g_data,
 };
 
        return ehl_pse0_common_data(pdev, plat);
 }
 
-static struct stmmac_pci_info ehl_pse0_sgmii1g_pci_info = {
+static struct stmmac_pci_info ehl_pse0_sgmii1g_info = {
        .setup = ehl_pse0_sgmii1g_data,
 };
 
        return ehl_pse1_common_data(pdev, plat);
 }
 
-static struct stmmac_pci_info ehl_pse1_rgmii1g_pci_info = {
+static struct stmmac_pci_info ehl_pse1_rgmii1g_info = {
        .setup = ehl_pse1_rgmii1g_data,
 };
 
        return ehl_pse1_common_data(pdev, plat);
 }
 
-static struct stmmac_pci_info ehl_pse1_sgmii1g_pci_info = {
+static struct stmmac_pci_info ehl_pse1_sgmii1g_info = {
        .setup = ehl_pse1_sgmii1g_data,
 };
 
        return tgl_common_data(pdev, plat);
 }
 
-static struct stmmac_pci_info tgl_sgmii1g_pci_info = {
+static struct stmmac_pci_info tgl_sgmii1g_info = {
        .setup = tgl_sgmii_data,
 };
 
        return 0;
 }
 
-static const struct stmmac_pci_info quark_pci_info = {
+static const struct stmmac_pci_info quark_info = {
        .setup = quark_default_data,
 };
 
        struct stmmac_resources res;
        int ret;
 
-       intel_priv = devm_kzalloc(&pdev->dev, sizeof(*intel_priv),
-                                 GFP_KERNEL);
+       intel_priv = devm_kzalloc(&pdev->dev, sizeof(*intel_priv), GFP_KERNEL);
        if (!intel_priv)
                return -ENOMEM;
 
 #define PCI_DEVICE_ID_INTEL_TGL_SGMII1G_ID             0xa0ac
 
 static const struct pci_device_id intel_eth_pci_id_table[] = {
-       { PCI_DEVICE_DATA(INTEL, QUARK_ID, &quark_pci_info) },
-       { PCI_DEVICE_DATA(INTEL, EHL_RGMII1G_ID, &ehl_rgmii1g_pci_info) },
-       { PCI_DEVICE_DATA(INTEL, EHL_SGMII1G_ID, &ehl_sgmii1g_pci_info) },
-       { PCI_DEVICE_DATA(INTEL, EHL_SGMII2G5_ID, &ehl_sgmii1g_pci_info) },
-       { PCI_DEVICE_DATA(INTEL, EHL_PSE0_RGMII1G_ID,
-                         &ehl_pse0_rgmii1g_pci_info) },
-       { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII1G_ID,
-                         &ehl_pse0_sgmii1g_pci_info) },
-       { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII2G5_ID,
-                         &ehl_pse0_sgmii1g_pci_info) },
-       { PCI_DEVICE_DATA(INTEL, EHL_PSE1_RGMII1G_ID,
-                         &ehl_pse1_rgmii1g_pci_info) },
-       { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII1G_ID,
-                         &ehl_pse1_sgmii1g_pci_info) },
-       { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII2G5_ID,
-                         &ehl_pse1_sgmii1g_pci_info) },
-       { PCI_DEVICE_DATA(INTEL, TGL_SGMII1G_ID, &tgl_sgmii1g_pci_info) },
+       { PCI_DEVICE_DATA(INTEL, QUARK_ID, &quark_info) },
+       { PCI_DEVICE_DATA(INTEL, EHL_RGMII1G_ID, &ehl_rgmii1g_info) },
+       { PCI_DEVICE_DATA(INTEL, EHL_SGMII1G_ID, &ehl_sgmii1g_info) },
+       { PCI_DEVICE_DATA(INTEL, EHL_SGMII2G5_ID, &ehl_sgmii1g_info) },
+       { PCI_DEVICE_DATA(INTEL, EHL_PSE0_RGMII1G_ID, &ehl_pse0_rgmii1g_info) },
+       { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII1G_ID, &ehl_pse0_sgmii1g_info) },
+       { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII2G5_ID, &ehl_pse0_sgmii1g_info) },
+       { PCI_DEVICE_DATA(INTEL, EHL_PSE1_RGMII1G_ID, &ehl_pse1_rgmii1g_info) },
+       { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII1G_ID, &ehl_pse1_sgmii1g_info) },
+       { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII2G5_ID, &ehl_pse1_sgmii1g_info) },
+       { PCI_DEVICE_DATA(INTEL, TGL_SGMII1G_ID, &tgl_sgmii1g_info) },
        {}
 };
-
 MODULE_DEVICE_TABLE(pci, intel_eth_pci_id_table);
 
 static struct pci_driver intel_eth_pci_driver = {