==================
In case you have questions about, problems with or contributions for
-PPCBoot you should send a message to the PPCBoot mailing list at
+PPCBoot you should send a message to the PPCBoot mailing list at
<ppcboot-users@lists.sourceforge.net>. There is also an archive of
previous traffic on the mailing list - please search the archive
before asking FAQ's. Please see
- board/cogent Files specific to Cogent boards
(need further configuration)
Files specific to CPCIISER4 boards
-- board/cu824 Files specific to CU824 boards
+- board/cu824 Files specific to CU824 boards
- board/eric Files specific to ERIC boards
- board/esd/ Files specific to boards manufactured by ESD
- board/esd/adciop Files specific to ADCIOP boards
-- board/esd/ar405 Files specific to AR405 boards
-- board/esd/canbt Files specific to CANBT boards
+- board/esd/ar405 Files specific to AR405 boards
+- board/esd/canbt Files specific to CANBT boards
- board/esd/cpci405 Files specific to CPCI405 boards
- board/esd/cpciiser4 Files specific to CPCIISER4 boards
- board/esd/common Common files for ESD boards
- board/evb64260
Files specific to EVB64260 boards
- board/fads Files specific to FADS boards
-- board/flagadm Files specific to FLAGADM boards
+- board/flagadm Files specific to FLAGADM boards
- board/genietv Files specific to GENIETV boards
-- board/gth Files specific to GTH boards
+- board/gth Files specific to GTH boards
- board/hermes Files specific to HERMES boards
- board/hymod Files specific to HYMOD boards
- board/ip860 Files specific to IP860 boards
- board/ivms8 Files specific to IVMS8/IVML24 boards
- board/lantec Files specific to LANTEC boards
-- board/lwmon Files specific to LWMON boards
+- board/lwmon Files specific to LWMON boards
- board/mbx8xx Files specific to MBX boards
- board/mpl/common Common files for MPL boards
- board/mpl/pip405 Files specific to PIP405 boards
- board/sandpoint
Files specific to Sandpoint boards
- board/siemens Files specific to boards manufactured by Siemens AG
-- board/siemens/CCM Files specific to CCM boards
-- board/siemens/pcu_e Files specific to PCU_E boards
-- board/sbc8260 Files specific to BC8260 boards
+- board/siemens/CCM Files specific to CCM boards
+- board/siemens/pcu_e Files specific to PCU_E boards
+- board/sbc8260 Files specific to BC8260 boards
- board/sixnet Files specific to SIXNET boards
- board/spd8xx Files specific to SPD8xxTS boards
-- board/tqm8260 Files specific to TQM8260 boards
+- board/tqm8260 Files specific to TQM8260 boards
- board/tqm8xx Files specific to TQM8xxL boards
- board/walnut405
Files specific to Walnut405 boards
a "rotator" |\-/|\-/
- MPC824X Family Member (if CONFIG_MPC824X is defined)
- Define exactly one of
- CONFIG_MPC8240, CONFIG_MPC8245
+ Define exactly one of
+ CONFIG_MPC8240, CONFIG_MPC8245
- 8xx CPU Options: (if using an 8xx cpu)
Define one or more of
- Clock Interface:
CONFIG_CLOCKS_IN_MHZ
- PPCBoot stores all clock information in Hz
- internally. For binary compatibility with older Linux
- kernels (which expect the clocks passed in the
- bd_info data to be in MHz) the environment variable
- "clocks_in_mhz" can be defined so that PPCBoot
- converts clock data to MHZ before passing it to the
- Linux kernel.
+ PPCBoot stores all clock information in Hz
+ internally. For binary compatibility with older Linux
+ kernels (which expect the clocks passed in the
+ bd_info data to be in MHz) the environment variable
+ "clocks_in_mhz" can be defined so that PPCBoot
+ converts clock data to MHZ before passing it to the
+ Linux kernel.
- When CONFIG_CLOCKS_IN_MHZ is defined, a definition of
- "clocks_in_mhz=1" is automatically included in the
- default environment.
+ When CONFIG_CLOCKS_IN_MHZ is defined, a definition of
+ "clocks_in_mhz=1" is automatically included in the
+ default environment.
- Console Interface:
Define exactly one of
CONFIG_SERIAL_SOFTWARE_FIFO
PPC405GP only.
- Use an interrupt handler for receiving data on the
- serial port. It also enables using hardware handshake
- (RTS/CTS) and UART's built-in FIFO. Set the number of
- bytes the interrupt driven input buffer should have.
+ Use an interrupt handler for receiving data on the
+ serial port. It also enables using hardware handshake
+ (RTS/CTS) and UART's built-in FIFO. Set the number of
+ bytes the interrupt driven input buffer should have.
Set to 0 to disable this feature (this is the default).
This will also disable hardware handshake.
- Pre-Boot Commands:
CONFIG_PREBOOT
- When this option is #defined, the existence of the
- environment variable "preboot" will be checked
- immediately before starting the CONFIG_BOOTDELAY
- countdown and/or running the auto-boot command resp.
- entering interactive mode.
+ When this option is #defined, the existence of the
+ environment variable "preboot" will be checked
+ immediately before starting the CONFIG_BOOTDELAY
+ countdown and/or running the auto-boot command resp.
+ entering interactive mode.
- This feature is especially useful when "preboot" is
- automatically generated or modified. For an example
- see the LWMON board specific code: here "preboot" is
- modified when the user holds down a certain
- combination of keys on the (special) keyboard when
- booting the systems
+ This feature is especially useful when "preboot" is
+ automatically generated or modified. For an example
+ see the LWMON board specific code: here "preboot" is
+ modified when the user holds down a certain
+ combination of keys on the (special) keyboard when
+ booting the systems
- Serial Download Echo Mode:
CONFIG_LOADS_ECHO
CFG_CMD_FDC * Floppy Disk Support
CFG_CMD_SCSI * SCSI Support
CFG_CMD_SETGETDCR Support for DCR Register access (4xx only)
- CFG_CMD_USB * USB support
- CFG_CMD_BSP * Board SPecific functions
+ CFG_CMD_USB * USB support
+ CFG_CMD_BSP * Board SPecific functions
-----------------------------------------------
CFG_CMD_ALL all
- Real-Time Clock:
- When CFG_CMD_DATE is selected, the type of the RTC
- has to be selected, too. Define exactly one of the
- following options:
+ When CFG_CMD_DATE is selected, the type of the RTC
+ has to be selected, too. Define exactly one of the
+ following options:
CONFIG_RTC_MPC8xx - use internal RTC of MPC8xx
CONFIG_RTC_PCF8563 - use Philips PCF8563 RTC
CONFIG_MAC_PARTITION and/or CONFIG_DOS_PARTITION
and/or CONFIG_ISO_PARTITION
- If IDE or SCSI support is enabled (CFG_CMD_IDE or
- CFG_CMD_SCSI) you must configure support for at least
- one partition type as well.
+ If IDE or SCSI support is enabled (CFG_CMD_IDE or
+ CFG_CMD_SCSI) you must configure support for at least
+ one partition type as well.
- IDE Reset method:
CONFIG_IDE_RESET_ROUTINE
- Set this to define that instead of a reset Pin, the
- routine ide_set_reset(int idereset) will be used.
+ Set this to define that instead of a reset Pin, the
+ routine ide_set_reset(int idereset) will be used.
- ATAPI Support:
CONFIG_ATAPI
Set this to enable ATAPI support.
- SCSI Support:
- At the moment only there is only support for the
- SYM53C8XX SCSI controller; define
- CONFIG_SCSI_SYM53C8XX to enable it.
+ At the moment only there is only support for the
+ SYM53C8XX SCSI controller; define
+ CONFIG_SCSI_SYM53C8XX to enable it.
- CFG_SCSI_MAX_LUN [8], CFG_SCSI_MAX_SCSI_ID [7] and
- CFG_SCSI_MAX_DEVICE [CFG_SCSI_MAX_SCSI_ID *
- CFG_SCSI_MAX_LUN] can be adjusted to define the
- maximum numbers of LUNs, SCSI ID's and target
- devices.
+ CFG_SCSI_MAX_LUN [8], CFG_SCSI_MAX_SCSI_ID [7] and
+ CFG_SCSI_MAX_DEVICE [CFG_SCSI_MAX_SCSI_ID *
+ CFG_SCSI_MAX_LUN] can be adjusted to define the
+ maximum numbers of LUNs, SCSI ID's and target
+ devices.
- USB Support:
- At the moment only the UHCI host controller is
- supported (PIP405, MIP405); define
+ At the moment only the UHCI host controller is
+ supported (PIP405, MIP405); define
CONFIG_USB_UHCI to enable it.
- define CONFIG_USB_KEYBOARD to enable the USB Keyboard
- end define CONFIG_USB_STORAGE to enable the USB
- storage devices.
- Note:
- Supported are USB Keyboards and USB Floppy drives
- (TEAC FD-05PUB).
+ define CONFIG_USB_KEYBOARD to enable the USB Keyboard
+ end define CONFIG_USB_STORAGE to enable the USB
+ storage devices.
+ Note:
+ Supported are USB Keyboards and USB Floppy drives
+ (TEAC FD-05PUB).
- Keyboard Support:
CONFIG_ISA_KEYBOARD
- Define this to enable standard (PC-Style) keyboard
+ Define this to enable standard (PC-Style) keyboard
support
- Video support:
CONFIG_VIDEO
- Define this to enable video support (for output to
- video).
+ Define this to enable video support (for output to
+ video).
CONFIG_VIDEO_CT69000
- LCD Support: CONFIG_LCD
- Define this to enable LCD support (for output to LCD
- display); also select one of the supported displays
- by defining one of these:
+ Define this to enable LCD support (for output to LCD
+ display); also select one of the supported displays
+ by defining one of these:
CONFIG_NEC_NL6648AC33:
- NEC NL6648AC33-18. Active, color, single scan.
+ NEC NL6648AC33-18. Active, color, single scan.
CONFIG_NEC_NL6648BC20
- NEC NL6648BC20-08. 6.5", 640x480.
+ NEC NL6648BC20-08. 6.5", 640x480.
Active, color, single scan.
CONFIG_SHARP_16x9
CONFIG_OPTREX_BW
- Optrex CBL50840-2 NF-FW 99 22 M5
+ Optrex CBL50840-2 NF-FW 99 22 M5
or
- Hitachi LMG6912RPFC-00T
+ Hitachi LMG6912RPFC-00T
or
- Hitachi SP14Q002
+ Hitachi SP14Q002
320x240. Black & white.
- Normally display is black on white background; define
- CFG_WHITE_ON_BLACK to get it inverted.
+ Normally display is black on white background; define
+ CFG_WHITE_ON_BLACK to get it inverted.
- Ethernet address:
CONFIG_ETHADDR
CONFIG_ETH2ADDR
CONFIG_ETH3ADDR
- Define a default value for ethernet address to use
- for the respective ethernet interface, in case this
- is not determined automatically.
+ Define a default value for ethernet address to use
+ for the respective ethernet interface, in case this
+ is not determined automatically.
- IP address:
CONFIG_IPADDR
- Define a default value for the IP address to use for
- the default ethernet interface, in case this is not
- determined through e.g. bootp.
+ Define a default value for the IP address to use for
+ the default ethernet interface, in case this is not
+ determined through e.g. bootp.
- Server IP address:
CONFIG_SERVERIP
- Defines a default value for theIP address of a TFTP
- server to contact when using the "tftboot" command.
+ Defines a default value for theIP address of a TFTP
+ server to contact when using the "tftboot" command.
- BOOTP Recovery Mode:
CONFIG_BOOTP_RANDOM_DELAY
- If you have many targets in a network that try to
- boot using BOOTP, you may want to avoid that all
- systems send out BOOTP requests at precisely the same
- moment (which would happen for instance at recovery
- from a power failure, when all systems will try to
- boot, thus flooding the BOOTP server. Defining
- CONFIG_BOOTP_RANDOM_DELAY causes a random delay to be
- inserted before sending out BOOTP requests. The
- following delays are insterted then:
+ If you have many targets in a network that try to
+ boot using BOOTP, you may want to avoid that all
+ systems send out BOOTP requests at precisely the same
+ moment (which would happen for instance at recovery
+ from a power failure, when all systems will try to
+ boot, thus flooding the BOOTP server. Defining
+ CONFIG_BOOTP_RANDOM_DELAY causes a random delay to be
+ inserted before sending out BOOTP requests. The
+ following delays are insterted then:
1st BOOTP request: delay 0 ... 1 sec
2nd BOOTP request: delay 0 ... 2 sec
- Status LED: CONFIG_STATUS_LED
- Several configurations allow to display the current
- status using a LED. For instance, the LED will blink
- fast while running PPCBoot code, stop blinking as
- soon as a reply to a BOOTP request was received, and
- start blinking slow once the Linux kernel is running
- (supported by a status LED driver in the Linux
- kernel). Defining CONFIG_STATUS_LED enables this
- feature in PPCBoot.
+ Several configurations allow to display the current
+ status using a LED. For instance, the LED will blink
+ fast while running PPCBoot code, stop blinking as
+ soon as a reply to a BOOTP request was received, and
+ start blinking slow once the Linux kernel is running
+ (supported by a status LED driver in the Linux
+ kernel). Defining CONFIG_STATUS_LED enables this
+ feature in PPCBoot.
- CAN Support: CONFIG_CAN_DRIVER
- Defining CONFIG_CAN_DRIVER enables CAN driver support
- on those systems that support this (optional)
- feature, like the TQM8xxL modules.
+ Defining CONFIG_CAN_DRIVER enables CAN driver support
+ on those systems that support this (optional)
+ feature, like the TQM8xxL modules.
- I2C Support: CONFIG_I2C
CONFIG_SOFT_I2C
- Use software (aka bit-banging) driver instead of CPM
- or similar hardware support for I2C
+ Use software (aka bit-banging) driver instead of CPM
+ or similar hardware support for I2C
- SPI Support: CONFIG_SPI
- Configuration Management:
CONFIG_IDENT_STRING
- If defined, this string will be added to the PPCBoot
- version information (PPCBOOT_VERSION)
+ If defined, this string will be added to the PPCBoot
+ version information (PPCBOOT_VERSION)
- Vendor Parameter Protection:
- PPCBoot considers the values of the environment
- variables "serial#" (Board Serial Number) and
- "ethaddr" (Ethernet Address) to bb parameters that
- are set once by the board vendor / manufacturer, and
- protects these variables from casual modification by
- the user. Once set, these variables are read-only,
- and write or delete attempts are rejected. You can
- change this behviour:
-
- If CONFIG_ENV_OVERWRITE is #defined in your config
- file, the write protection for vendor parameters is
- completely disabled. Anybody can change or delte
- these parameters.
-
- Alternatively, if you #define _both_ CONFIG_ETHADDR
- _and_ CONFIG_OVERWRITE_ETHADDR_ONCE, a default
- ethernet address is installed in the environment,
- which can be changed exactly ONCE by the user. [The
- serial# is unaffected by this, i. e. it remains
- read-only.]
+ PPCBoot considers the values of the environment
+ variables "serial#" (Board Serial Number) and
+ "ethaddr" (Ethernet Address) to bb parameters that
+ are set once by the board vendor / manufacturer, and
+ protects these variables from casual modification by
+ the user. Once set, these variables are read-only,
+ and write or delete attempts are rejected. You can
+ change this behviour:
+
+ If CONFIG_ENV_OVERWRITE is #defined in your config
+ file, the write protection for vendor parameters is
+ completely disabled. Anybody can change or delte
+ these parameters.
+
+ Alternatively, if you #define _both_ CONFIG_ETHADDR
+ _and_ CONFIG_OVERWRITE_ETHADDR_ONCE, a default
+ ethernet address is installed in the environment,
+ which can be changed exactly ONCE by the user. [The
+ serial# is unaffected by this, i. e. it remains
+ read-only.]
- Protected RAM:
CONFIG_PRAM
- Define this variable to enable the reservation of
- "protected RAM", i. e. RAM which is not overwritten
- by PPCBoot. Define CONFIG_PRAM to hold the number of
- kB you want to reserve for pRAM. You can overwrite
- this default value by defining an environment
- variable "pram" to the number of kB you want to
- reserve. Note that the board info structure will
- still show the full amount of RAM. If pRAM is
- reserved, a new environment variable "mem" will
- automatically be defined to hold the amount of
- remaining RAM in a form that can be passed as boot
- argument to Linux, for instance like that:
+ Define this variable to enable the reservation of
+ "protected RAM", i. e. RAM which is not overwritten
+ by PPCBoot. Define CONFIG_PRAM to hold the number of
+ kB you want to reserve for pRAM. You can overwrite
+ this default value by defining an environment
+ variable "pram" to the number of kB you want to
+ reserve. Note that the board info structure will
+ still show the full amount of RAM. If pRAM is
+ reserved, a new environment variable "mem" will
+ automatically be defined to hold the amount of
+ remaining RAM in a form that can be passed as boot
+ argument to Linux, for instance like that:
setenv bootargs ... mem=\$(mem)
saveenv
- This way you can tell Linux not to use this memory,
- either, which results in a memory region that will
- not be affected by reboots.
+ This way you can tell Linux not to use this memory,
+ either, which results in a memory region that will
+ not be affected by reboots.
- *WARNING* If your board configuration uses automatic
- detection of the RAM size, you must make sure that
- this memory test is non-destructive. So far, the
- following board configurations are known to be
- "pRAM-clean":
+ *WARNING* If your board configuration uses automatic
+ detection of the RAM size, you must make sure that
+ this memory test is non-destructive. So far, the
+ following board configurations are known to be
+ "pRAM-clean":
ETX094, IVMS8, IVML24, SPD8xx, TQM8xxL,
HERMES, IP860, RPXlite, LWMON, LANTEC,
- Error Recovery:
CONFIG_PANIC_HANG
- Define this variable to stop the system in case of a
- fatal error, so that you have to reset it manually.
- This is probably NOT a good idea for an embedded
- system where you want to system to reboot
- automatically as fast as possible, but it may be
- useful during development since you can try to debug
- the conditions that lead to the situation.
+ Define this variable to stop the system in case of a
+ fatal error, so that you have to reset it manually.
+ This is probably NOT a good idea for an embedded
+ system where you want to system to reboot
+ automatically as fast as possible, but it may be
+ useful during development since you can try to debug
+ the conditions that lead to the situation.
- Command Interpreter:
CFG_HUSH_PARSER
- Define this variable to enable the "hush" shell (from
- Busybox) as command line interpreter, thus enabling
- powerful command line syntax like
- if...then...else...fi conditionals or `&&' and '||'
- constructs ("shell scripts").
+ Define this variable to enable the "hush" shell (from
+ Busybox) as command line interpreter, thus enabling
+ powerful command line syntax like
+ if...then...else...fi conditionals or `&&' and '||'
+ constructs ("shell scripts").
- If undefined, you get the old, much simpler behaviour
+ If undefined, you get the old, much simpler behaviour
with a somewhat smapper memory footprint.
CFG_PROMPT_HUSH_PS2
- This defines the secondary prompt string, which is
- printed when the command interpreter needs more input
- to complete a command. Usually "> ".
+ This defines the secondary prompt string, which is
+ printed when the command interpreter needs more input
+ to complete a command. Usually "> ".
Note:
- In the current implementation, the local variables
- space and global environment variables space are
- separated. Local variables are those you define by
- simply typing like `name=value'. To access a local
- variable later on, you have write `$name' or
- `${name}'; variable directly by typing say `$name' at
- the command prompt.
+ In the current implementation, the local variables
+ space and global environment variables space are
+ separated. Local variables are those you define by
+ simply typing like `name=value'. To access a local
+ variable later on, you have write `$name' or
+ `${name}'; variable directly by typing say `$name' at
+ the command prompt.
- Global environment variables are those you use
- setenv/printenv to work with. To run a command stored
- in such a variable, you need to use the run command,
- and you must not use the '$' sign to access them.
+ Global environment variables are those you use
+ setenv/printenv to work with. To run a command stored
+ in such a variable, you need to use the run command,
+ and you must not use the '$' sign to access them.
- To store commands and special characters in a
- variable, please use double quotation marks
- surrounding the whole text of the variable, instead
- of the backslashes before semicolons and special
- symbols.
+ To store commands and special characters in a
+ variable, please use double quotation marks
+ surrounding the whole text of the variable, instead
+ of the backslashes before semicolons and special
+ symbols.
Configuration Settings:
- CFG_DIRECT_FLASH_TFTP:
- Enable TFTP transfers directly to flash memory;
- without this option such a download has to be
- performed in two steps: (1) download to RAM, and (2)
- copy from RAM to flash.
+ Enable TFTP transfers directly to flash memory;
+ without this option such a download has to be
+ performed in two steps: (1) download to RAM, and (2)
+ copy from RAM to flash.
- The two-step approach is usually more reliable, since
- you can check if the download worked before you erase
- the flash, but in some situations (when sytem RAM is
- too limited to allow for a tempory copy of the
- downloaded image) this option may be very useful.
+ The two-step approach is usually more reliable, since
+ you can check if the download worked before you erase
+ the flash, but in some situations (when sytem RAM is
+ too limited to allow for a tempory copy of the
+ downloaded image) this option may be very useful.
The following definitions that deal with the placement and management
- CFG_SPI_INIT_OFFSET
- Defines offset to the initial SPI buffer area in DPRAM. The
- area is used at an early stage (ROM part) if the environment
- is configured to reside in the SPI EEPROM: We need a 520 byte
- scratch DPRAM area. It is used between the two initialization
- calls (spi_init_f() and spi_init_r()). A value of 0xB00 seems
- to be a good choice since it makes it far enough from the
- start of the data area as well as from the stack pointer.
+ Defines offset to the initial SPI buffer area in DPRAM. The
+ area is used at an early stage (ROM part) if the environment
+ is configured to reside in the SPI EEPROM: We need a 520 byte
+ scratch DPRAM area. It is used between the two initialization
+ calls (spi_init_f() and spi_init_r()). A value of 0xB00 seems
+ to be a good choice since it makes it far enough from the
+ start of the data area as well as from the stack pointer.
Please note that the environment is read-only as long as the monitor
has been relocated to RAM and a RAM copy of the environment has been
Cache Line Size of the CPU.
- CFG_DEFAULT_IMMR:
- Default address of the IMMR after system reset.
- Needed on some 8260 systems (MPC8260ADS and RPXsuper)
- to be able to adjust the position of the IMMR
- register after a reset.
+ Default address of the IMMR after system reset.
+ Needed on some 8260 systems (MPC8260ADS and RPXsuper)
+ to be able to adjust the position of the IMMR
+ register after a reset.
- CFG_IMMR: Physical address of the Internal Memory Mapped
Register; DO NOT CHANGE! (11-4)
- CFG_INIT_RAM_ADDR:
- Start address of memory area tha can be used for
- initial data and stack; please note that this mus be
- writable memory that is working WITHOUT special
- initialization, i. e. you CANNOT use normal RAM which
- will become available only after programming the
- memory controller and running certain initialization
- sequences.
+ Start address of memory area tha can be used for
+ initial data and stack; please note that this mus be
+ writable memory that is working WITHOUT special
+ initialization, i. e. you CANNOT use normal RAM which
+ will become available only after programming the
+ memory controller and running certain initialization
+ sequences.
PPCBoot uses the following memory types:
- - MPC8xx and MPC8260: IMMR (internal memory of the CPU)
- - MPC824X: data cache
+ - MPC8xx and MPC8260: IMMR (internal memory of the CPU)
+ - MPC824X: data cache
+ - PPC4xx: data cache
- CFG_INIT_DATA_OFFSET:
- Offset of the initial data structure in the memory
- area defined by CFG_INIT_RAM_ADDR. Usually
- CFG_INIT_DATA_OFFSET is chosen such that the initial
- data is located at the end of the available space
- (sometimes written as (CFG_INIT_RAM_END -
- CFG_INIT_DATA_SIZE), and the initial stack is just
- below that area (growing from (CFG_INIT_RAM_ADDR +
- CFG_INIT_DATA_OFFSET) downward.
+ Offset of the initial data structure in the memory
+ area defined by CFG_INIT_RAM_ADDR. Usually
+ CFG_INIT_DATA_OFFSET is chosen such that the initial
+ data is located at the end of the available space
+ (sometimes written as (CFG_INIT_RAM_END -
+ CFG_INIT_DATA_SIZE), and the initial stack is just
+ below that area (growing from (CFG_INIT_RAM_ADDR +
+ CFG_INIT_DATA_OFFSET) downward.
Note:
- On the MPC824X (or other systems that use the data
- cache for initial memory) the address chosen for
- CFG_INIT_RAM_ADDR is basically arbitrary - it must
- point to an otherwise UNUSED address space between
- the top of RAM and the start of the PCI space.
+ On the MPC824X (or other systems that use the data
+ cache for initial memory) the address chosen for
+ CFG_INIT_RAM_ADDR is basically arbitrary - it must
+ point to an otherwise UNUSED address space between
+ the top of RAM and the start of the PCI space.
- CFG_SIUMCR: SIU Module Configuration (11-6)
define relocation offset in DPRAM [SCC4]
- CFG_USE_OSCCLK:
- Use OSCM clock mode on MBX8xx board. Be careful,
- wrong setting might damage your board. Read
- doc/README.MBX before setting this variable!
+ Use OSCM clock mode on MBX8xx board. Be careful,
+ wrong setting might damage your board. Read
+ doc/README.MBX before setting this variable!
Building the Software:
======================
where "NAME_config" is the name of one of the existing
configurations; the following names are supported:
- ADCIOP_config GTH_config TQM850L_config
- ADS860_config IP860_config TQM855L_config
- AR405_config IVML24_config TQM860L_config
- CANBT_config IVMS8_config WALNUT405_config
- CPCI405_config LANTEC_config cogent_common_config
- CPCIISER4_config MBX_config cogent_mpc8260_config
- CU824_config MBX860T_config cogent_mpc8xx_config
- ESTEEM192E_config RPXlite_config hermes_config
- ETX094_config RPXsuper_config hymod_config
- FADS823_config SM850_config lwmon_config
- FADS850SAR_config SPD823TS_config pcu_e_config
- FADS860T_config SXNI855T_config rsdproto_config
- FPS850L_config Sandpoint8240_config sbc8260_config
- GENIETV_config TQM823L_config PIP405_config
+ ADCIOP_config GTH_config TQM850L_config
+ ADS860_config IP860_config TQM855L_config
+ AR405_config IVML24_config TQM860L_config
+ CANBT_config IVMS8_config WALNUT405_config
+ CPCI405_config LANTEC_config cogent_common_config
+ CPCIISER4_config MBX_config cogent_mpc8260_config
+ CU824_config MBX860T_config cogent_mpc8xx_config
+ ESTEEM192E_config RPXlite_config hermes_config
+ ETX094_config RPXsuper_config hymod_config
+ FADS823_config SM850_config lwmon_config
+ FADS850SAR_config SPD823TS_config pcu_e_config
+ FADS860T_config SXNI855T_config rsdproto_config
+ FPS850L_config Sandpoint8240_config sbc8260_config
+ GENIETV_config TQM823L_config PIP405_config
Note: for some board special configuration names may exist; check if
additional information is available from the board vendor; for
instance, the TQM8xxL systems run normally at 50 MHz and use a
- SCC for 10baseT ethernet; there are also systems with 80 MHz
- CPU clock, and an optional Fast Ethernet module is available
+ SCC for 10baseT ethernet; there are also systems with 80 MHz
+ CPU clock, and an optional Fast Ethernet module is available
for CPU's with FEC. You can select such additional "features"
when chosing the configuration, i. e.
make TQM860L_config
- - will configure for a plain TQM860L, i. e. 50MHz, no FEC
+ - will configure for a plain TQM860L, i. e. 50MHz, no FEC
make TQM860L_FEC_config
- - will configure for a TQM860L at 50MHz with FEC for ethernet
+ - will configure for a TQM860L at 50MHz with FEC for ethernet
make TQM860L_80MHz_config
- - will configure for a TQM860L at 80 MHz, with normal 10baseT
+ - will configure for a TQM860L at 80 MHz, with normal 10baseT
interface
make TQM860L_FEC_80MHz_config
- - will configure for a TQM860L at 80 MHz with FEC for ethernet
+ - will configure for a TQM860L at 80 MHz with FEC for ethernet
make TQM823L_LCD_config
- - will configure for a TQM823L with PPCBoot console on LCD
+ - will configure for a TQM823L with PPCBoot console on LCD
make TQM823L_LCD_80MHz_config
- - will configure for a TQM823L at 80 MHz with PPCBoot console on LCD
+ - will configure for a TQM823L at 80 MHz with PPCBoot console on LCD
etc.
Testing of PPCBoot Modifications, Ports to New Hardware, etc.:
==============================================================
-If you have modified PPCBoot sources (for instance added a new board
-or support for new devices, a new CPU, etc.) you are expected to
+If you have modified PPCBoot sources (for instance added a new board
+or support for new devices, a new CPU, etc.) you are expected to
provide feedback to the other developers. The feedback normally takes
the form of a "patch", i. e. a context diff against a certain (latest
official or latest in CVS) version of PPCBoot sources.
-But before you submit such a patch, please verify that your modifi-
-cation did not break existing code. At least make sure that *ALL* of
+But before you submit such a patch, please verify that your modifi-
+cation did not break existing code. At least make sure that *ALL* of
the supported boards compile WITHOUT ANY compiler warnings. To do so,
just run the "MAKEALL" script, which will configure and build PPCBoot
for ALL supported system. Be warned, this will take a while. You can
-select which (cross) compiler to use py passing a `CROSS_COMPILE'
+select which (cross) compiler to use py passing a `CROSS_COMPILE'
environment variable to the script, i. e. to use the cross tools from
MontaVista's Hard Hat Linux you can type
/*
- * (C) Copyright 2001
+ * (C) Copyright 2001, 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* High Level Configuration Options
* (easy to change)
***********************************************************/
-#define CONFIG_405GP 1 /* This is a PPC405 CPU */
-#define CONFIG_4xx 1 /* ...member of PPC4xx family */
-#define CONFIG_MIP405 1 /* ...on a MIP405 board */
+#define CONFIG_405GP 1 /* This is a PPC405 CPU */
+#define CONFIG_4xx 1 /* ...member of PPC4xx family */
+#define CONFIG_MIP405 1 /* ...on a MIP405 board */
/***********************************************************
* Clock
***********************************************************/
-#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
+#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
/***********************************************************
* Command definitions
***********************************************************/
#define CONFIG_COMMANDS \
- (CONFIG_CMD_DFL | \
+ (CONFIG_CMD_DFL | \
CFG_CMD_IDE | \
CFG_CMD_DHCP | \
CFG_CMD_PCI | \
CFG_CMD_IRQ | \
CFG_CMD_EEPROM | \
CFG_CMD_I2C | \
- CFG_CMD_REGINFO | \
+ CFG_CMD_REGINFO | \
CFG_CMD_DATE | \
CFG_CMD_ELF | \
CFG_CMD_USB | \
CFG_CMD_MII | \
+ CFG_CMD_DOC | \
CFG_CMD_BSP )
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
-#define CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
/**************************************************************
* I2C Stuff:
* the PIP405 is equiped with an Atmel 24C128/256 EEPROM at address
* EEPROM of the SDRAM
* The Atmel EEPROM uses 16Bit addressing.
***************************************************************/
-#define CONFIG_I2C405
+#define CONFIG_I2C405
#define CONFIG_I2C
#define CONFIG_I2C_X
-#define CFG_I2C_EEPROM_ADDR 0x53
-#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET 0x00000 /* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE 0x00800 /* 2k bytes may be used for env vars */
+#define CFG_I2C_EEPROM_ADDR 0x53
+#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET 0x00000 /* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE 0x00800 /* 2k bytes may be used for env vars */
/* The Atmel 24C128/256 has 64 byte page write mode using last 6 bits of the address */
-#define CFG_EEPROM_PAGE_WRITE_BITS 6
-#define CFG_EEPROM_PAGE_WRITE_ENABLE /* enable Page write */
+#define CFG_EEPROM_PAGE_WRITE_BITS 6
+#define CFG_EEPROM_PAGE_WRITE_ENABLE /* enable Page write */
/***************************************************************
* Definitions for Serial Presence Detect EEPROM address
* (to get SDRAM settings)
***************************************************************/
-#define SDRAM_EEPROM_WRITE_ADDRESS 0xA0
-#define SDRAM_EEPROM_READ_ADDRESS 0xA1
+#define SDRAM_EEPROM_WRITE_ADDRESS 0xA0
+#define SDRAM_EEPROM_READ_ADDRESS 0xA1
/**************************************************************
* Environment definitions
**************************************************************/
#define CONFIG_BAUDRATE 9600 /* STD Baudrate */
-#define CONFIG_BOOTDELAY 5
+#define CONFIG_BOOTDELAY 5
/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
#define CONFIG_BOOTCOMMAND "diskboot 200000 0:1; bootm" /* autoboot command */
#define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
-#define CONFIG_IPADDR 10.0.0.100
+#define CONFIG_IPADDR 10.0.0.100
#define CONFIG_SERVERIP 10.0.0.1
/***************************************************************
/***********************************************************
* Miscellaneous configurable options
**********************************************************/
-#define CFG_LONGHELP /* undef to save memory */
+#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x0100000 /* memtest works on */
#define CFG_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */
-#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
+#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
#define CFG_IGNORE_405_UART_ERRATA_59
/* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE \
- { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
- 57600, 115200, 230400, 460800, 921600 }
+#define CFG_BAUDRATE_TABLE \
+ { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
+ 57600, 115200, 230400, 460800, 921600 }
-#define CFG_LOAD_ADDR 0x200000 /* default load address */
-#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+#define CFG_LOAD_ADDR 0x200000 /* default load address */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
*/
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_HOST /* configure as pci-host */
-#define CONFIG_PCI_PNP /* pci plug-and-play */
- /* resource configuration */
-#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
-#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
-#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
-#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
-#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
+#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_HOST /* configure as pci-host */
+#define CONFIG_PCI_PNP /* pci plug-and-play */
+ /* resource configuration */
+#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
+#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
+#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
+#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
+#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
+#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
/*
* Init Memory Controller:
- */
+ */
#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
#define OCM_DATA_ADDR 0xF0000000
/* Peripheral Bus Mapping */
-#define PER_PLD_ADDR 0xF4000000 /* smallest window is 1MByte 0x10 0000*/
-#define PER_UART0_ADDR 0xF4100000 /* smallest window is 1MByte 0x10 0000*/
-#define PER_UART1_ADDR 0xF4200000 /* smallest window is 1MByte 0x10 0000*/
+#define PER_PLD_ADDR 0xF4000000 /* smallest window is 1MByte 0x10 0000*/
+#define PER_UART0_ADDR 0xF4100000 /* smallest window is 1MByte 0x10 0000*/
+#define PER_UART1_ADDR 0xF4200000 /* smallest window is 1MByte 0x10 0000*/
#define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in On Chip SRAM)
*/
-#define CFG_INIT_RAM_ADDR OCM_DATA_ADDR /* inside of On Chip SRAM */
-#define CFG_INIT_RAM_END 0x1000 /* End of On Chip SRAM */
-#define CFG_INIT_DATA_SIZE 64 /* size in bytes reserved for initial data */
+#define CFG_INIT_RAM_ADDR OCM_DATA_ADDR /* inside of On Chip SRAM */
+#define CFG_INIT_RAM_END 0x1000 /* End of On Chip SRAM */
+#define CFG_INIT_DATA_SIZE 64 /* size in bytes reserved for initial data */
#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_INIT_DATA_OFFSET
* Ethernet Stuff
***********************************************************/
#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 1 /* PHY address */
+#define CONFIG_PHY_ADDR 1 /* PHY address */
/************************************************************
* RTC
#define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */
#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
-#define CFG_ATA_BASE_ADDR CFG_ISA_IO_BASE_ADDRESS /* base address */
-#define CFG_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
-#define CFG_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */
-#define CFG_ATA_DATA_OFFSET 0 /* data reg offset */
-#define CFG_ATA_REG_OFFSET 0 /* reg offset */
+#define CFG_ATA_BASE_ADDR CFG_ISA_IO_BASE_ADDRESS /* base address */
+#define CFG_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
+#define CFG_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */
+#define CFG_ATA_DATA_OFFSET 0 /* data reg offset */
+#define CFG_ATA_REG_OFFSET 0 /* reg offset */
#define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */
-#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */
-#undef CONFIG_IDE_LED /* no led for ide supported */
-#define CONFIG_IDE_RESET /* reset for ide supported... */
+#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */
+#undef CONFIG_IDE_LED /* no led for ide supported */
+#define CONFIG_IDE_RESET /* reset for ide supported... */
#define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
/************************************************************
#undef CONFIG_SCSI_SYM53C8XX
#ifdef CONFIG_SCSI_SYM53C8XX
-#define CFG_SCSI_MAX_LUN 8 /* number of supported LUNs */
+#define CFG_SCSI_MAX_LUN 8 /* number of supported LUNs */
#define CFG_SCSI_MAX_SCSI_ID 7 /* maximum SCSI ID (0..6) */
-#define CFG_SCSI_MAX_DEVICE CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN /* maximum Target devices */
+#define CFG_SCSI_MAX_DEVICE CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN /* maximum Target devices */
#endif /* CONFIG_SCSI_SYM53C8XX */
/************************************************************
* DISK Partition support
#define CONFIG_MAC_PARTITION
#define CONFIG_ISO_PARTITION /* Experimental */
+/************************************************************
+ * Disk-On-Chip configuration
+ ************************************************************/
+#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
+#define CFG_DOC_SHORT_TIMEOUT
+#define CFG_DOC_SUPPORT_2000
+#define CFG_DOC_SUPPORT_MILLENNIUM
/************************************************************
* Keyboard support
************************************************************/
* High Level Configuration Options
* (easy to change)
***********************************************************/
-#define CONFIG_405GP 1 /* This is a PPC405 CPU */
-#define CONFIG_4xx 1 /* ...member of PPC4xx family */
-#define CONFIG_PIP405 1 /* ...on a PIP405 board */
+#define CONFIG_405GP 1 /* This is a PPC405 CPU */
+#define CONFIG_4xx 1 /* ...member of PPC4xx family */
+#define CONFIG_PIP405 1 /* ...on a PIP405 board */
/***********************************************************
* Clock
***********************************************************/
-#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
+#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
/***********************************************************
* Command definitions
***********************************************************/
#define CONFIG_COMMANDS \
- (CONFIG_CMD_DFL | \
+ (CONFIG_CMD_DFL | \
CFG_CMD_IDE | \
CFG_CMD_DHCP | \
CFG_CMD_PCI | \
CFG_CMD_IRQ | \
CFG_CMD_EEPROM | \
CFG_CMD_I2C | \
- CFG_CMD_REGINFO | \
+ CFG_CMD_REGINFO | \
CFG_CMD_FDC | \
CFG_CMD_SCSI | \
CFG_CMD_DATE | \
CFG_CMD_ELF | \
CFG_CMD_USB | \
CFG_CMD_MII | \
+ CFG_CMD_DOC | \
CFG_CMD_BSP )
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
-#define CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
/**************************************************************
* I2C Stuff:
* the PIP405 is equiped with an Atmel 24C128/256 EEPROM at address
***************************************************************/
#define CONFIG_I2C_X
#define CONFIG_I2C405
-#define CFG_I2C_EEPROM_ADDR 0x53
-#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE 0x200 /* 512 bytes may be used for env vars */
+#define CFG_I2C_EEPROM_ADDR 0x53
+#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE 0x200 /* 512 bytes may be used for env vars */
/* The Atmel 24C128/256 has 64 byte page write mode using last 6 bits of the address */
-#define CFG_EEPROM_PAGE_WRITE_BITS 6
-#define CFG_EEPROM_PAGE_WRITE_ENABLE /* enable Page write */
+#define CFG_EEPROM_PAGE_WRITE_BITS 6
+#define CFG_EEPROM_PAGE_WRITE_ENABLE /* enable Page write */
/***************************************************************
* Definitions for Serial Presence Detect EEPROM address
* (to get SDRAM settings)
***************************************************************/
-#define SDRAM_EEPROM_WRITE_ADDRESS 0xA0
-#define SDRAM_EEPROM_READ_ADDRESS 0xA1
+#define SDRAM_EEPROM_WRITE_ADDRESS 0xA0
+#define SDRAM_EEPROM_READ_ADDRESS 0xA1
#define CONFIG_BOARD_PRE_INIT
/**************************************************************
#define CONFIG_BAUDRATE 9600 /* STD Baudrate */
-#define CONFIG_BOOTDELAY 5
+#define CONFIG_BOOTDELAY 5
/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
#define CONFIG_BOOTCOMMAND "diskboot 200000 0:1; bootm" /* autoboot command */
#define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
-#define CONFIG_IPADDR 10.0.0.100
+#define CONFIG_IPADDR 10.0.0.100
#define CONFIG_SERVERIP 10.0.0.1
/***************************************************************
/***********************************************************
* Miscellaneous configurable options
**********************************************************/
-#define CFG_LONGHELP /* undef to save memory */
+#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x0100000 /* memtest works on */
#define CFG_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */
-#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
+#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
#define CFG_IGNORE_405_UART_ERRATA_59
/* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE \
- { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
- 57600, 115200, 230400, 460800, 921600 }
+#define CFG_BAUDRATE_TABLE \
+ { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
+ 57600, 115200, 230400, 460800, 921600 }
#define CFG_LOAD_ADDR 0x200000 /* default load address */
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
*/
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_HOST /* configure as pci-host */
-#define CONFIG_PCI_PNP /* pci plug-and-play */
- /* resource configuration */
-#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
-#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
-#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
-#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
-#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
+#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_HOST /* configure as pci-host */
+#define CONFIG_PCI_PNP /* pci plug-and-play */
+ /* resource configuration */
+#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
+#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
+#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
+#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
+#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
+#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
*/
#define CFG_INIT_RAM_ADDR OCM_DATA_ADDR /* inside of On Chip SRAM */
#define CFG_INIT_RAM_END 0x1000 /* End of On Chip SRAM */
-#define CFG_INIT_DATA_SIZE 64 /* size in bytes reserved for initial data */
+#define CFG_INIT_DATA_SIZE 64 /* size in bytes reserved for initial data */
#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_INIT_DATA_OFFSET
* Ethernet Stuff
***********************************************************/
#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 1 /* PHY address */
-
+#define CONFIG_PHY_ADDR 1 /* PHY address */
+#define CONFIG_CS8952_PHY 1 /* its a CS8952 PHY */
/************************************************************
* RTC
***********************************************************/
#define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */
#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
-#define CFG_ATA_BASE_ADDR CFG_ISA_IO_BASE_ADDRESS /* base address */
-#define CFG_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
-#define CFG_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */
-#define CFG_ATA_DATA_OFFSET 0 /* data reg offset */
-#define CFG_ATA_REG_OFFSET 0 /* reg offset */
-#define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */
+#define CFG_ATA_BASE_ADDR CFG_ISA_IO_BASE_ADDRESS /* base address */
+#define CFG_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
+#define CFG_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */
+#define CFG_ATA_DATA_OFFSET 0 /* data reg offset */
+#define CFG_ATA_REG_OFFSET 0 /* reg offset */
+#define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */
-#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */
-#undef CONFIG_IDE_LED /* no led for ide supported */
-#define CONFIG_IDE_RESET /* reset for ide supported... */
-#define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
+#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */
+#undef CONFIG_IDE_LED /* no led for ide supported */
+#define CONFIG_IDE_RESET /* reset for ide supported... */
+#define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
/************************************************************
* ATAPI support (experimental)
* SCSI support (experimental) only SYM53C8xx supported
************************************************************/
#define CONFIG_SCSI_SYM53C8XX
-#define CFG_SCSI_MAX_LUN 8 /* number of supported LUNs */
-#define CFG_SCSI_MAX_SCSI_ID 7 /* maximum SCSI ID (0..6) */
-#define CFG_SCSI_MAX_DEVICE CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN /* maximum Target devices */
+#define CFG_SCSI_MAX_LUN 8 /* number of supported LUNs */
+#define CFG_SCSI_MAX_SCSI_ID 7 /* maximum SCSI ID (0..6) */
+#define CFG_SCSI_MAX_DEVICE CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN /* maximum Target devices */
+
+/************************************************************
+ * Disk-On-Chip configuration
+ ************************************************************/
+#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
+#define CFG_DOC_SHORT_TIMEOUT
+#define CFG_DOC_SUPPORT_2000
+#define CFG_DOC_SUPPORT_MILLENNIUM
/************************************************************
* DISK Partition support
projects / users / rw / ppcboot.git / commitdiff