drm/amdgpu: disable clock/power gating for SRIOV

and disable MC resum in VCN2.0 as well
those are not concerned by VF driver

Singed-off-by: darlington Opara <darlington.opara@amd.com>
Signed-off-by: Jinage Zhao <jiange.zhao@amd.com>
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index dd500d1064a8549144bd2e6243c5c847b12be278..f2745fd1ddb36dd7ed8a0582e73c9c0d2c133577 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -320,6 +320,9 @@ static void vcn_v2_0_mc_resume(struct amdgpu_device *adev)
        uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
        uint32_t offset;
 
+       if (amdgpu_sriov_vf(adev))
+               return;
+
        /* cache window 0: fw */
        if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
                WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
@@ -464,6 +467,9 @@ static void vcn_v2_0_disable_clock_gating(struct amdgpu_device *adev)
 {
        uint32_t data;
 
+       if (amdgpu_sriov_vf(adev))
+               return;
+
        /* UVD disable CGC */
        data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
        if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
@@ -622,6 +628,9 @@ static void vcn_v2_0_enable_clock_gating(struct amdgpu_device *adev)
 {
        uint32_t data = 0;
 
+       if (amdgpu_sriov_vf(adev))
+               return;
+
        /* enable UVD CGC */
        data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
        if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
@@ -674,6 +683,9 @@ static void vcn_v2_0_disable_static_power_gating(struct amdgpu_device *adev)
        uint32_t data = 0;
        int ret;
 
+       if (amdgpu_sriov_vf(adev))
+               return;
+
        if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
                data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
                        | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
@@ -721,6 +733,9 @@ static void vcn_v2_0_enable_static_power_gating(struct amdgpu_device *adev)
        uint32_t data = 0;
        int ret;
 
+       if (amdgpu_sriov_vf(adev))
+               return;
+
        if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
                /* Before power off, this indicator has to be turned on */
                data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
@@ -1231,6 +1246,9 @@ static int vcn_v2_0_set_clockgating_state(void *handle,
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
        bool enable = (state == AMD_CG_STATE_GATE);
 
+       if (amdgpu_sriov_vf(adev))
+               return 0;
+
        if (enable) {
                /* wait for STATUS to clear */
                if (vcn_v2_0_is_idle(handle))
@@ -1686,6 +1704,11 @@ static int vcn_v2_0_set_powergating_state(void *handle,
        int ret;
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
+       if (amdgpu_sriov_vf(adev)) {
+               adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
+               return 0;
+       }
+
        if (state == adev->vcn.cur_state)
                return 0;