drm/amd/display: Add hubp_init entry to hubp vtable

Different HW will need to init HUBP differently. For now, add a vtable
entry, and hook a NO-OP for DCN1.

In addition, future HW will need to access the HUBPREQ_DEBUG register
for hubp_init. Add it to the reg list.

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
index 683829466a44c4279db97fbb72338fef9851b404..787a36566fb9a7bb615d552998ed04bb5f5a88fa 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
@@ -1197,6 +1197,10 @@ void hubp1_vtg_sel(struct hubp *hubp, uint32_t otg_inst)
        REG_UPDATE(DCHUBP_CNTL, HUBP_VTG_SEL, otg_inst);
 }
 
+void hubp1_init(struct hubp *hubp)
+{
+       //do nothing
+}
 static const struct hubp_funcs dcn10_hubp_funcs = {
        .hubp_program_surface_flip_and_addr =
                        hubp1_program_surface_flip_and_addr,
@@ -1220,7 +1224,7 @@ static const struct hubp_funcs dcn10_hubp_funcs = {
        .hubp_clear_underflow = hubp1_clear_underflow,
        .hubp_disable_control =  hubp1_disable_control,
        .hubp_get_underflow_status = hubp1_get_underflow_status,
-
+       .hubp_init = hubp1_init,
 };
 
 /*****************************************/

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
index db98ba361686a8d51b9d3f44fac5b2f958758265..99d2b7e2a578984fcb610027e9e321ebdd82edfa 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
@@ -34,6 +34,7 @@
 #define HUBP_REG_LIST_DCN(id)\
        SRI(DCHUBP_CNTL, HUBP, id),\
        SRI(HUBPREQ_DEBUG_DB, HUBP, id),\
+       SRI(HUBPREQ_DEBUG, HUBP, id),\
        SRI(DCSURF_ADDR_CONFIG, HUBP, id),\
        SRI(DCSURF_TILING_CONFIG, HUBP, id),\
        SRI(DCSURF_SURFACE_PITCH, HUBPREQ, id),\
@@ -138,6 +139,7 @@
 #define HUBP_COMMON_REG_VARIABLE_LIST \
        uint32_t DCHUBP_CNTL; \
        uint32_t HUBPREQ_DEBUG_DB; \
+       uint32_t HUBPREQ_DEBUG; \
        uint32_t DCSURF_ADDR_CONFIG; \
        uint32_t DCSURF_TILING_CONFIG; \
        uint32_t DCSURF_SURFACE_PITCH; \
@@ -749,4 +751,6 @@ enum cursor_pitch hubp1_get_cursor_pitch(unsigned int pitch);
 void hubp1_vready_workaround(struct hubp *hubp,
                struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest);
 
+void hubp1_init(struct hubp *hubp);
+
 #endif

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 7e173c74907c7e3dee77675553896e626352a0d8..33d311cea28cd3c8856898ac9fe41d92627a78b6 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1123,6 +1123,7 @@ static void dcn10_init_hw(struct dc *dc)
                        struct hubp *hubp = dc->res_pool->hubps[i];
                        struct dpp *dpp = dc->res_pool->dpps[i];
 
+                       hubp->funcs->hubp_init(hubp);
                        dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
                        plane_atomic_power_down(dc, dpp, hubp);
                }

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
index 1cd07e94ee63184de3f1338887b456cb4cfab147..455df4999797f21797426ea20e2a156ce57070a7 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
@@ -130,6 +130,7 @@ struct hubp_funcs {
        void (*hubp_clear_underflow)(struct hubp *hubp);
        void (*hubp_disable_control)(struct hubp *hubp, bool disable_hubp);
        unsigned int (*hubp_get_underflow_status)(struct hubp *hubp);
+       void (*hubp_init)(struct hubp *hubp);
 
 };