size);
 }
 
+int hl_fw_send_soft_reset(struct hl_device *hdev)
+{
+       struct cpucp_packet pkt;
+       int rc;
+
+       memset(&pkt, 0, sizeof(pkt));
+       pkt.ctl = cpu_to_le32(CPUCP_PACKET_SOFT_RESET << CPUCP_PKT_CTL_OPCODE_SHIFT);
+       rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), 0, NULL);
+       if (rc)
+               dev_err(hdev->dev, "failed to send soft-reset msg (err = %d)\n", rc);
+
+       return rc;
+}
+
 int hl_fw_send_device_activity(struct hl_device *hdev, bool open)
 {
        struct cpucp_packet pkt;
 
 int hl_fw_dram_pending_row_get(struct hl_device *hdev, u32 *pend_rows_num);
 int hl_fw_cpucp_engine_core_asid_set(struct hl_device *hdev, u32 asid);
 int hl_fw_send_device_activity(struct hl_device *hdev, bool open);
+int hl_fw_send_soft_reset(struct hl_device *hdev);
 int hl_pci_bars_map(struct hl_device *hdev, const char * const name[3],
                        bool is_wc[3]);
 int hl_pci_elbi_read(struct hl_device *hdev, u64 addr, u32 *data);
 
                                                u32 poll_timeout_us)
 {
        struct cpu_dyn_regs *dyn_regs = &hdev->fw_loader.dynamic_loader.comm_desc.cpu_dyn_regs;
+       int rc = 0;
 
        if (!driver_performs_reset) {
-               /* set SP to indicate reset request sent to FW */
-               if (dyn_regs->cpu_rst_status)
-                       WREG32(le32_to_cpu(dyn_regs->cpu_rst_status), CPU_RST_STATUS_NA);
-               else
-                       WREG32(mmCPU_RST_STATUS_TO_HOST, CPU_RST_STATUS_NA);
-
-               WREG32(le32_to_cpu(dyn_regs->gic_host_soft_rst_irq),
-                       gaudi2_irq_map_table[GAUDI2_EVENT_CPU_SOFT_RESET].cpu_id);
-
-               return gaudi2_get_soft_rst_done_indication(hdev, poll_timeout_us);
+               if (hl_is_fw_sw_ver_below(hdev, 1, 10)) {
+                       /* set SP to indicate reset request sent to FW */
+                       if (dyn_regs->cpu_rst_status)
+                               WREG32(le32_to_cpu(dyn_regs->cpu_rst_status), CPU_RST_STATUS_NA);
+                       else
+                               WREG32(mmCPU_RST_STATUS_TO_HOST, CPU_RST_STATUS_NA);
+                       WREG32(le32_to_cpu(dyn_regs->gic_host_soft_rst_irq),
+                               gaudi2_irq_map_table[GAUDI2_EVENT_CPU_SOFT_RESET].cpu_id);
+
+                       /* wait for f/w response */
+                       rc = gaudi2_get_soft_rst_done_indication(hdev, poll_timeout_us);
+               } else {
+                       rc = hl_fw_send_soft_reset(hdev);
+               }
+               return rc;
        }
 
        /* Block access to engines, QMANs and SM during reset, these
 
  *
  * CPUCP_PACKET_REGISTER_INTERRUPTS -
  *       Packet to register interrupts indicating LKD is ready to receive events from FW.
+ *
+ * CPUCP_PACKET_SOFT_RESET -
+ *      Packet to perform soft-reset.
  */
 
 enum cpucp_packet_id {
        CPUCP_PACKET_RESERVED11,                /* not used */
        CPUCP_PACKET_RESERVED12,                /* internal */
        CPUCP_PACKET_REGISTER_INTERRUPTS,       /* internal */
+       CPUCP_PACKET_SOFT_RESET,                /* internal */
        CPUCP_PACKET_ID_MAX                     /* must be last */
 };