/* Enable the module */
ret = regmap_set_bits(micfil->regmap, REG_MICFIL_CTRL1,
- MICFIL_CTRL1_PDMIEN);
+ MICFIL_CTRL1_PDMIEN | MICFIL_CTRL1_ERREN);
if (ret)
return ret;
/* Disable the module */
ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
- MICFIL_CTRL1_PDMIEN);
+ MICFIL_CTRL1_PDMIEN | MICFIL_CTRL1_ERREN);
if (ret)
return ret;
{
switch (reg) {
case REG_MICFIL_STAT:
+ case REG_MICFIL_FIFO_STAT:
case REG_MICFIL_DATACH0:
case REG_MICFIL_DATACH1:
case REG_MICFIL_DATACH2:
case REG_MICFIL_DATACH5:
case REG_MICFIL_DATACH6:
case REG_MICFIL_DATACH7:
+ case REG_MICFIL_OUT_STAT:
case REG_MICFIL_VERID:
case REG_MICFIL_PARAM:
case REG_MICFIL_VAD0_STAT:
{
struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
struct platform_device *pdev = micfil->pdev;
+ u32 fifo_stat_reg;
+ u32 out_stat_reg;
u32 stat_reg;
regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg);
MICFIL_STAT_LOWFREQF, MICFIL_STAT_LOWFREQF);
}
+ regmap_read(micfil->regmap, REG_MICFIL_FIFO_STAT, &fifo_stat_reg);
+ regmap_write_bits(micfil->regmap, REG_MICFIL_FIFO_STAT,
+ fifo_stat_reg, fifo_stat_reg);
+
+ regmap_read(micfil->regmap, REG_MICFIL_OUT_STAT, &out_stat_reg);
+ regmap_write_bits(micfil->regmap, REG_MICFIL_OUT_STAT,
+ out_stat_reg, out_stat_reg);
+
return IRQ_HANDLED;
}