powerpc: Don't hard code the size of pte page

USE PTRS_PER_PTE to indicate the size of pte page. To support THP,
later patches will be changing PTRS_PER_PTE value.

Acked-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

diff --git a/arch/powerpc/include/asm/pgtable.h b/arch/powerpc/include/asm/pgtable.h
index a9cbd3ba5c33936d8c1885e33bd60450adb52998..4b52726e01ca5cea007cb745a9508a83f13f33b1 100644 (file)
--- a/arch/powerpc/include/asm/pgtable.h
+++ b/arch/powerpc/include/asm/pgtable.h
@@ -17,6 +17,12 @@ struct mm_struct;
 #  include <asm/pgtable-ppc32.h>
 #endif
 
+/*
+ * We save the slot number & secondary bit in the second half of the
+ * PTE page. We use the 8 bytes per each pte entry.
+ */
+#define PTE_PAGE_HIDX_OFFSET (PTRS_PER_PTE * 8)
+
 #ifndef __ASSEMBLY__
 
 #include <asm/tlbflush.h>

diff --git a/arch/powerpc/mm/hash_low_64.S b/arch/powerpc/mm/hash_low_64.S
index 7443481a315c4922063a5f8801c62ee9bfb7691f..abdd5e21cdb68787c9bacd0d8d9b838bbb4bb1fb 100644 (file)
--- a/arch/powerpc/mm/hash_low_64.S
+++ b/arch/powerpc/mm/hash_low_64.S
@@ -490,7 +490,7 @@ END_FTR_SECTION(CPU_FTR_NOEXECUTE|CPU_FTR_COHERENT_ICACHE, CPU_FTR_NOEXECUTE)
        beq     htab_inval_old_hpte
 
        ld      r6,STK_PARAM(R6)(r1)
-       ori     r26,r6,0x8000           /* Load the hidx mask */
+       ori     r26,r6,PTE_PAGE_HIDX_OFFSET /* Load the hidx mask. */
        ld      r26,0(r26)
        addi    r5,r25,36               /* Check actual HPTE_SUB bit, this */
        rldcr.  r0,r31,r5,0             /* must match pgtable.h definition */
@@ -607,7 +607,7 @@ htab_pte_insert_ok:
        sld     r4,r4,r5
        andc    r26,r26,r4
        or      r26,r26,r3
-       ori     r5,r6,0x8000
+       ori     r5,r6,PTE_PAGE_HIDX_OFFSET
        std     r26,0(r5)
        lwsync
        std     r30,0(r6)