mac_mode = MAC_MODE_PORT_MODE_TBI;
                }
 
-               if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
-                   GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752)
+               if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
                        tw32(MAC_LED_CTRL, tp->led_ctrl);
 
                if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
                tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
                if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
                        tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
-                       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
-                           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
+                       if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
                                tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
                }
        }
        tw32(GRC_MISC_CFG, val);
 
        /* Initialize MBUF/DESC pool. */
-       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
-           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
+       if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
                /* Do nothing.  */
        } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
                tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
                tw32(NVRAM_CFG1, nvcfg1);
        }
 
-       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
-           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
+       if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
                switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
                        case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
                                tp->nvram_jedecnum = JEDEC_ATMEL;
            GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
                tp->tg3_flags |= TG3_FLAG_NVRAM;
 
-               if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
-                   GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
+               if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
                        u32 nvaccess = tr32(NVRAM_ACCESS);
 
                        tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
                tg3_get_nvram_info(tp);
                tg3_get_nvram_size(tp);
 
-               if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
-                   GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
+               if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
                        u32 nvaccess = tr32(NVRAM_ACCESS);
 
                        tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
 
        tg3_nvram_lock(tp);
 
-       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
-           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
+       if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
                u32 nvaccess = tr32(NVRAM_ACCESS);
 
                tw32_f(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
 
        tg3_nvram_unlock(tp);
 
-       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
-           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
+       if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
                u32 nvaccess = tr32(NVRAM_ACCESS);
 
                tw32_f(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
 
                tg3_nvram_lock(tp);
 
-               if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
-                   GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
+               if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
                        u32 nvaccess = tr32(NVRAM_ACCESS);
 
                        tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
                grc_mode = tr32(GRC_MODE);
                tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
 
-               if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
-                   GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
+               if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
                        u32 nvaccess = tr32(NVRAM_ACCESS);
 
                        tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
                } else
                        eeprom_phy_id = 0;
 
-               if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
-                   GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
+               if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
                        led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
                                    SHASTA_EXT_LED_MODE_MASK);
-               } else
+               else
                        led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
 
                switch (led_cfg) {
 
                if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
                        tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
-                       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
-                           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
+                       if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
                                tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
                }
                if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)