drm/amd/display: Ammend DCPG IP control sequences to align with HW guidance

[WHY&HOW]
IP_REQUEST_CNTL should only be toggled off when it was originally, never
unconditionally.

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
index a5e18ab72394ae63344f35fe9864757d827d6d1f..dec732c0c59c87d2254be964ecae1b22319ba52b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
@@ -1266,14 +1266,18 @@ static void dcn20_power_on_plane_resources(
        struct dce_hwseq *hws,
        struct pipe_ctx *pipe_ctx)
 {
+       uint32_t org_ip_request_cntl = 0;
+
        DC_LOGGER_INIT(hws->ctx->logger);
 
        if (hws->funcs.dpp_root_clock_control)
                hws->funcs.dpp_root_clock_control(hws, pipe_ctx->plane_res.dpp->inst, true);
 
        if (REG(DC_IP_REQUEST_CNTL)) {
-               REG_SET(DC_IP_REQUEST_CNTL, 0,
-                               IP_REQUEST_EN, 1);
+               REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
+               if (org_ip_request_cntl == 0)
+                       REG_SET(DC_IP_REQUEST_CNTL, 0,
+                                       IP_REQUEST_EN, 1);
 
                if (hws->funcs.dpp_pg_control)
                        hws->funcs.dpp_pg_control(hws, pipe_ctx->plane_res.dpp->inst, true);
@@ -1281,8 +1285,10 @@ static void dcn20_power_on_plane_resources(
                if (hws->funcs.hubp_pg_control)
                        hws->funcs.hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, true);
 
-               REG_SET(DC_IP_REQUEST_CNTL, 0,
-                               IP_REQUEST_EN, 0);
+               if (org_ip_request_cntl == 0)
+                       REG_SET(DC_IP_REQUEST_CNTL, 0,
+                                       IP_REQUEST_EN, 0);
+
                DC_LOG_DEBUG(
                                "Un-gated front end for pipe %d\n", pipe_ctx->plane_res.hubp->inst);
        }

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
index 92bb820817b9dc375170d54eb9c1f56009645dd1..8ad0ff669b7aab750dfbaeb8f88096ed250e0984 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
@@ -2610,3 +2610,37 @@ void dcn401_detect_pipe_changes(struct dc_state *old_state,
                new_pipe->update_flags.bits.test_pattern_changed = 1;
        }
 }
+
+void dcn401_plane_atomic_power_down(struct dc *dc,
+               struct dpp *dpp,
+               struct hubp *hubp)
+{
+       struct dce_hwseq *hws = dc->hwseq;
+       uint32_t org_ip_request_cntl = 0;
+
+       DC_LOGGER_INIT(dc->ctx->logger);
+
+       REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
+       if (org_ip_request_cntl == 0)
+               REG_SET(DC_IP_REQUEST_CNTL, 0,
+                       IP_REQUEST_EN, 1);
+
+       if (hws->funcs.dpp_pg_control)
+               hws->funcs.dpp_pg_control(hws, dpp->inst, false);
+
+       if (hws->funcs.hubp_pg_control)
+               hws->funcs.hubp_pg_control(hws, hubp->inst, false);
+
+       hubp->funcs->hubp_reset(hubp);
+       dpp->funcs->dpp_reset(dpp);
+
+       if (org_ip_request_cntl == 0)
+               REG_SET(DC_IP_REQUEST_CNTL, 0,
+                       IP_REQUEST_EN, 0);
+
+       DC_LOG_DEBUG(
+                       "Power gated front end %d\n", hubp->inst);
+
+       if (hws->funcs.dpp_root_clock_control)
+               hws->funcs.dpp_root_clock_control(hws, dpp->inst, false);
+}

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h
index 17cea748789e183b0701884076cb6ee7ef03eb59..dbd69d215b8bc0cc97530446a226ca1971092f4c 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h
@@ -102,4 +102,7 @@ void dcn401_detect_pipe_changes(
        struct dc_state *new_state,
        struct pipe_ctx *old_pipe,
        struct pipe_ctx *new_pipe);
+void dcn401_plane_atomic_power_down(struct dc *dc,
+               struct dpp *dpp,
+               struct hubp *hubp);
 #endif /* __DC_HWSS_DCN401_H__ */

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c
index 44cb376f97c172e15c3425de0931e41434fbef36..a4e3501fadbbe08070d3b797d1516d74568d647a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c
@@ -123,7 +123,7 @@ static const struct hwseq_private_funcs dcn401_private_funcs = {
        .disable_vga = dcn20_disable_vga,
        .bios_golden_init = dcn10_bios_golden_init,
        .plane_atomic_disable = dcn20_plane_atomic_disable,
-       .plane_atomic_power_down = dcn10_plane_atomic_power_down,
+       .plane_atomic_power_down = dcn401_plane_atomic_power_down,
        .enable_power_gating_plane = dcn32_enable_power_gating_plane,
        .hubp_pg_control = dcn32_hubp_pg_control,
        .program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree,