drm/amdgpu/display: fix build without CONFIG_DRM_AMD_DC_DCN3_0

Need to guard some new DCN3.0 stuff.

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
index 43d0b4e53b5ded4dcbb2d2ca877dac28cff591ca..2972392f9788ab32c34e29ca78d26a47129f7356 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
@@ -288,13 +288,16 @@ void optc1_program_timing(
        if (optc1_is_two_pixels_per_containter(&patched_crtc_timing) || optc1->opp_count == 2)
                h_div = H_TIMING_DIV_BY2;
 
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
        if (optc1->tg_mask->OTG_H_TIMING_DIV_MODE != 0) {
                if (optc1->opp_count == 4)
                        h_div = H_TIMING_DIV_BY4;
 
                REG_UPDATE(OTG_H_TIMING_CNTL,
                OTG_H_TIMING_DIV_MODE, h_div);
-       } else {
+       } else
+#endif
+       {
                REG_UPDATE(OTG_H_TIMING_CNTL,
                OTG_H_TIMING_DIV_BY2, h_div);
        }