net: mv643xx_eth: proper initialization for Kirkwood SoCs

Ethernet controllers found on Kirkwood SoCs not only suffer from loosing
MAC address register contents on clock gating but also some important
registers are reset to values that would break ethernet. This patch
clears the CLK125_BYPASS_EN bit for DT enabled Kirkwood only by using
of_device_is_compatible() instead of #ifdefs. Non-DT Kirkwood is not
affected as it installs a clock gating workaround because of the MAC
address issue above. Other Orion SoCs do not suffer from register reset,
do not have the bit in question, or do not have the register at all.
Moreover, system controllers on PPC using this driver should also be
protected from clearing that bit.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/marvell/mv643xx_eth.c b/drivers/net/ethernet/marvell/mv643xx_eth.c
index 4f17d398a8ae9eead7fc9538aad915087bf2afef..1b31d752ff90a26a65cac5395ee3ee7ab5c45c6a 100644 (file)
--- a/drivers/net/ethernet/marvell/mv643xx_eth.c
+++ b/drivers/net/ethernet/marvell/mv643xx_eth.c
@@ -116,6 +116,8 @@ static char mv643xx_eth_driver_version[] = "1.4";
 #define  LINK_UP                       0x00000002
 #define TXQ_COMMAND                    0x0048
 #define TXQ_FIX_PRIO_CONF              0x004c
+#define PORT_SERIAL_CONTROL1           0x004c
+#define  CLK125_BYPASS_EN              0x00000010
 #define TX_BW_RATE                     0x0050
 #define TX_BW_MTU                      0x0058
 #define TX_BW_BURST                    0x005c
@@ -2701,6 +2703,15 @@ static int mv643xx_eth_probe(struct platform_device *pdev)
 
        mp->dev = dev;
 
+       /* Kirkwood resets some registers on gated clocks. Especially
+        * CLK125_BYPASS_EN must be cleared but is not available on
+        * all other SoCs/System Controllers using this driver.
+        */
+       if (of_device_is_compatible(pdev->dev.of_node,
+                                   "marvell,kirkwood-eth-port"))
+               wrlp(mp, PORT_SERIAL_CONTROL1,
+                    rdlp(mp, PORT_SERIAL_CONTROL1) & ~CLK125_BYPASS_EN);
+
        /*
         * Start with a default rate, and if there is a clock, allow
         * it to override the default.