#define GENI_OUTPUT_CTRL               0x24
 #define GENI_CGC_CTRL                  0x28
 #define GENI_CLK_CTRL_RO               0x60
-#define GENI_IF_DISABLE_RO             0x64
 #define GENI_FW_S_REVISION_RO          0x6c
 #define SE_GENI_BYTE_GRAN              0x254
 #define SE_GENI_TX_PACKING_CFG0                0x260
 
 #define SE_GENI_STATUS                 0x40
 #define GENI_SER_M_CLK_CFG             0x48
 #define GENI_SER_S_CLK_CFG             0x4c
+#define GENI_IF_DISABLE_RO             0x64
 #define GENI_FW_REVISION_RO            0x68
 #define SE_GENI_CLK_SEL                        0x7c
 #define SE_GENI_DMA_MODE_EN            0x258
 #define CLK_DIV_MSK                    GENMASK(15, 4)
 #define CLK_DIV_SHFT                   4
 
+/* GENI_IF_DISABLE_RO fields */
+#define FIFO_IF_DISABLE                        (BIT(0))
+
 /* GENI_FW_REVISION_RO fields */
 #define FW_REV_PROTOCOL_MSK            GENMASK(15, 8)
 #define FW_REV_PROTOCOL_SHFT           8