drm/i915/gen11: Program the chroma upsampler for HDR planes.

We configure the chroma upsampler with the same chroma siting as
used by the scaler for consistency, the chroma upsampler is used
instead of the scaler for YUV 4:2:0 on ICL's HDR planes.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181018115134.9061-7-maarten.lankhorst@linux.intel.com

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fae316f93c2bc020ad7b3dfe9d54e36ffb1e2308..57068aee8211dc98f12e502fc067d34bd75334e0 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6550,6 +6550,19 @@ enum {
 #define _PLANE_AUX_DIST_2_A                    0x702c0
 #define _PLANE_AUX_OFFSET_1_A                  0x701c4
 #define _PLANE_AUX_OFFSET_2_A                  0x702c4
+#define _PLANE_CUS_CTL_1_A                     0x701c8
+#define _PLANE_CUS_CTL_2_A                     0x702c8
+#define  PLANE_CUS_ENABLE                      (1 << 31)
+#define  PLANE_CUS_PLANE_6                     (0 << 30)
+#define  PLANE_CUS_PLANE_7                     (1 << 30)
+#define  PLANE_CUS_HPHASE_SIGN_NEGATIVE                (1 << 19)
+#define  PLANE_CUS_HPHASE_0                    (0 << 16)
+#define  PLANE_CUS_HPHASE_0_25                 (1 << 16)
+#define  PLANE_CUS_HPHASE_0_5                  (2 << 16)
+#define  PLANE_CUS_VPHASE_SIGN_NEGATIVE                (1 << 15)
+#define  PLANE_CUS_VPHASE_0                    (0 << 12)
+#define  PLANE_CUS_VPHASE_0_25                 (1 << 12)
+#define  PLANE_CUS_VPHASE_0_5                  (2 << 12)
 #define _PLANE_COLOR_CTL_1_A                   0x701CC /* GLK+ */
 #define _PLANE_COLOR_CTL_2_A                   0x702CC /* GLK+ */
 #define _PLANE_COLOR_CTL_3_A                   0x703CC /* GLK+ */
@@ -6687,6 +6700,15 @@ enum {
 #define PLANE_AUX_OFFSET(pipe, plane)   \
        _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
 
+#define _PLANE_CUS_CTL_1_B             0x711c8
+#define _PLANE_CUS_CTL_2_B             0x712c8
+#define _PLANE_CUS_CTL_1(pipe)       \
+               _PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B)
+#define _PLANE_CUS_CTL_2(pipe)       \
+               _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B)
+#define PLANE_CUS_CTL(pipe, plane)   \
+       _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe))
+
 #define _PLANE_COLOR_CTL_1_B                   0x711CC
 #define _PLANE_COLOR_CTL_2_B                   0x712CC
 #define _PLANE_COLOR_CTL_3_B                   0x713CC

diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 6b1cadfee6c2dd45b27e152f77f712f811c08328..95d9405f7e4da436d4994520bbe9ff1c2241968c 100644 (file)
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -380,6 +380,7 @@ skl_update_plane(struct intel_plane *plane,
        uint32_t y = plane_state->color_plane[0].y;
        uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
        uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
+       struct intel_plane *linked = plane_state->linked_plane;
        unsigned long irqflags;
        u32 keymsk = 0, keymax = 0;
 
@@ -417,6 +418,27 @@ skl_update_plane(struct intel_plane *plane,
                      (plane_state->color_plane[1].y << 16) |
                      plane_state->color_plane[1].x);
 
+       if (icl_is_hdr_plane(plane)) {
+               u32 cus_ctl = 0;
+
+               if (linked) {
+                       /* Enable and use MPEG-2 chroma siting */
+                       cus_ctl = PLANE_CUS_ENABLE |
+                               PLANE_CUS_HPHASE_0 |
+                               PLANE_CUS_VPHASE_SIGN_NEGATIVE |
+                               PLANE_CUS_VPHASE_0_25;
+
+                       if (linked->id == PLANE_SPRITE5)
+                               cus_ctl |= PLANE_CUS_PLANE_7;
+                       else if (linked->id == PLANE_SPRITE4)
+                               cus_ctl |= PLANE_CUS_PLANE_6;
+                       else
+                               MISSING_CASE(linked->id);
+               }
+
+               I915_WRITE_FW(PLANE_CUS_CTL(pipe, plane_id), cus_ctl);
+       }
+
        /* program plane scaler */
        if (plane_state->scaler_id >= 0) {
                skl_program_scaler(dev_priv, plane, crtc_state, plane_state);