ret = clk_prepare_enable(priv->clk_usb_general);
        if (ret) {
                dev_err(&phy->dev, "Failed to enable USB general clock\n");
+               reset_control_rearm(priv->reset);
                return ret;
        }
 
        if (ret) {
                dev_err(&phy->dev, "Failed to enable USB DDR clock\n");
                clk_disable_unprepare(priv->clk_usb_general);
+               reset_control_rearm(priv->reset);
                return ret;
        }
 
                                dev_warn(&phy->dev, "USB ID detect failed!\n");
                                clk_disable_unprepare(priv->clk_usb);
                                clk_disable_unprepare(priv->clk_usb_general);
+                               reset_control_rearm(priv->reset);
                                return -EINVAL;
                        }
                }
 
        clk_disable_unprepare(priv->clk_usb);
        clk_disable_unprepare(priv->clk_usb_general);
+       reset_control_rearm(priv->reset);
 
        /* power off the PHY by putting it into reset mode */
        regmap_update_bits(priv->regmap, REG_CTRL, REG_CTRL_POWER_ON_RESET,