drm/i915/psr: Disable PSR2 when SDP is sent on prior line

Selective update doesn't work if SU start address is 0 and start/end
SDP is configured to be sent prior to SU start/end lines. PSR2 has to be
disabled in this case for Alder Lake.

HSDES: 22012279113

Cc: Mika Kahola <mika.kahola@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220905102355.176622-3-jouni.hogander@intel.com
Reviewed-by: Mika Kahola <mika.kahola@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 6f03bf16d6f43092a88e2c8b96119f9d49e7cbf3..90d7cdd743beec6da97e04d426021b3293fac671 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -811,7 +811,8 @@ static bool _compute_psr2_sdp_prior_scanline_indication(struct intel_dp *intel_d
        if ((hblank_ns - req_ns) > 100)
                return true;
 
-       if (DISPLAY_VER(dev_priv) < 13 || intel_dp->edp_dpcd[0] < DP_EDP_14b)
+       /* Not supported <13 / Wa_22012279113:adl-p */
+       if (DISPLAY_VER(dev_priv) <= 13 || intel_dp->edp_dpcd[0] < DP_EDP_14b)
                return false;
 
        crtc_state->req_psr2_sdp_prior_scanline = true;