#define AMDGPU_TTM_VRAM_MAX_DW_READ    (size_t)128
 
+static int amdgpu_ttm_backend_bind(struct ttm_bo_device *bdev,
+                                  struct ttm_tt *ttm,
+                                  struct ttm_resource *bo_mem);
+
 static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev,
                                    unsigned int type,
                                    uint64_t size)
                goto out_cleanup;
 
        /* Bind the memory to the GTT space */
-       r = ttm_bo_tt_bind(bo, &tmp_mem);
+       r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, &tmp_mem);
        if (unlikely(r)) {
                goto out_cleanup;
        }
 
 #include <nvif/if500b.h>
 #include <nvif/if900b.h>
 
+static int nouveau_ttm_tt_bind(struct ttm_bo_device *bdev, struct ttm_tt *ttm,
+                              struct ttm_resource *reg);
+
 /*
  * NV10-NV40 tiling helpers
  */
        if (ret)
                goto out;
 
-       ret = ttm_bo_tt_bind(bo, &tmp_reg);
+       ret = nouveau_ttm_tt_bind(bo->bdev, bo->ttm, &tmp_reg);
        if (ret)
                goto out;
 
 
 static int radeon_ttm_debugfs_init(struct radeon_device *rdev);
 static void radeon_ttm_debugfs_fini(struct radeon_device *rdev);
 
+static int radeon_ttm_tt_bind(struct ttm_bo_device *bdev,
+                             struct ttm_tt *ttm,
+                             struct ttm_resource *bo_mem);
+
 struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev)
 {
        struct radeon_mman *mman;
                goto out_cleanup;
        }
 
-       r = ttm_bo_tt_bind(bo, &tmp_mem);
+       r = radeon_ttm_tt_bind(bo->bdev, bo->ttm, &tmp_mem);
        if (unlikely(r)) {
                goto out_cleanup;
        }
 
 {
        return bo->bdev->driver->ttm_tt_bind(bo->bdev, bo->ttm, mem);
 }
-EXPORT_SYMBOL(ttm_bo_tt_bind);
 
 void ttm_bo_tt_unbind(struct ttm_buffer_object *bo)
 {