drm/amdgpu: implement hdp v4_0 ras functions

implement hdp v4_0 ras functions, including
ras init/fini, query/reset_error_counter

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: John Clements <John.Clements@amd.com>
Reviewed-by: Dennis Li <Dennis.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
index edbd35d293ebfe83d766de96f2343ddd7d6fc62e..330c0f0e00b880741afee411d88538ae8322a345 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
@@ -59,12 +59,31 @@ static void hdp_v4_0_invalidate_hdp(struct amdgpu_device *adev,
                        HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
 }
 
+static void hdp_v4_0_query_ras_error_count(struct amdgpu_device *adev,
+                                          void *ras_error_status)
+{
+       struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
+
+       err_data->ue_count = 0;
+       err_data->ce_count = 0;
+
+       if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP))
+               return;
+
+       /* HDP SRAM errors are uncorrectable ones (i.e. fatal errors) */
+       err_data->ue_count += RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT);
+};
+
 static void hdp_v4_0_reset_ras_error_count(struct amdgpu_device *adev)
 {
        if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP))
                return;
-       /*read back hdp ras counter to reset it to 0 */
-       RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT);
+
+       if (adev->asic_type >= CHIP_ALDEBARAN)
+               WREG32_SOC15(HDP, 0, mmHDP_EDC_CNT, 0);
+       else
+               /*read back hdp ras counter to reset it to 0 */
+               RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT);
 }
 
 static void hdp_v4_0_update_clock_gating(struct amdgpu_device *adev,
@@ -130,6 +149,13 @@ static void hdp_v4_0_init_registers(struct amdgpu_device *adev)
        WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40));
 }
 
+const struct amdgpu_hdp_ras_funcs hdp_v4_0_ras_funcs = {
+       .ras_late_init = amdgpu_hdp_ras_late_init,
+       .ras_fini = amdgpu_hdp_ras_fini,
+       .query_ras_error_count = hdp_v4_0_query_ras_error_count,
+       .reset_ras_error_count = hdp_v4_0_reset_ras_error_count,
+};
+
 const struct amdgpu_hdp_funcs hdp_v4_0_funcs = {
        .flush_hdp = hdp_v4_0_flush_hdp,
        .invalidate_hdp = hdp_v4_0_invalidate_hdp,

diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.h b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.h
index d1e6399e8c46ef9e86cf9e521f11bbdf73474a26..dc3a1b81dd62bbccd33adea191bec8da235391b6 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.h
@@ -27,5 +27,6 @@
 #include "soc15_common.h"
 
 extern const struct amdgpu_hdp_funcs hdp_v4_0_funcs;
+extern const struct amdgpu_hdp_ras_funcs hdp_v4_0_ras_funcs;
 
 #endif