It doesn't make sense for a perf event to be configured as a CHAIN event
in isolation, so extend the arm_pmu structure with a ->filter_match()
function to allow the backend PMU implementation to reject CHAIN events
early.
Cc: <stable@vger.kernel.org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
        return 0;
 }
 
+static int armv8pmu_filter_match(struct perf_event *event)
+{
+       unsigned long evtype = event->hw.config_base & ARMV8_PMU_EVTYPE_EVENT;
+       return evtype != ARMV8_PMUV3_PERFCTR_CHAIN;
+}
+
 static void armv8pmu_reset(void *info)
 {
        struct arm_pmu *cpu_pmu = (struct arm_pmu *)info;
        cpu_pmu->stop                   = armv8pmu_stop,
        cpu_pmu->reset                  = armv8pmu_reset,
        cpu_pmu->set_event_filter       = armv8pmu_set_event_filter;
+       cpu_pmu->filter_match           = armv8pmu_filter_match;
 
        return 0;
 }
 
 {
        struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
        unsigned int cpu = smp_processor_id();
-       return cpumask_test_cpu(cpu, &armpmu->supported_cpus);
+       int ret;
+
+       ret = cpumask_test_cpu(cpu, &armpmu->supported_cpus);
+       if (ret && armpmu->filter_match)
+               return armpmu->filter_match(event);
+
+       return ret;
 }
 
 static ssize_t armpmu_cpumask_show(struct device *dev,
 
        void            (*stop)(struct arm_pmu *);
        void            (*reset)(void *);
        int             (*map_event)(struct perf_event *event);
+       int             (*filter_match)(struct perf_event *event);
        int             num_events;
        bool            secure_access; /* 32-bit ARM only */
 #define ARMV8_PMUV3_MAX_COMMON_EVENTS 0x40