ARM: fix cacheflush with PAN

It seems that the cacheflush syscall got broken when PAN for LPAE was
implemented. User access was not enabled around the cache maintenance
instructions, causing them to fault.

Fixes: 7af5b901e847 ("ARM: 9358/2: Implement PAN for LPAE by TTBR0 page table walks disablement")
Reported-by: Michał Pecio <michal.pecio@gmail.com>
Tested-by: Michał Pecio <michal.pecio@gmail.com>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>

diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index 480e307501bb4b3ff102bd9497664655f4d62661..6ea645939573fb65ed36f5435a9c94e98828f45b 100644 (file)
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -570,6 +570,7 @@ static int bad_syscall(int n, struct pt_regs *regs)
 static inline int
 __do_cache_op(unsigned long start, unsigned long end)
 {
+       unsigned int ua_flags;
        int ret;
 
        do {
@@ -578,7 +579,9 @@ __do_cache_op(unsigned long start, unsigned long end)
                if (fatal_signal_pending(current))
                        return 0;
 
+               ua_flags = uaccess_save_and_enable();
                ret = flush_icache_user_range(start, start + chunk);
+               uaccess_restore(ua_flags);
                if (ret)
                        return ret;