clk: sunxi-ng: a64: force select PLL_MIPI in TCON0 mux

TCON0's source clock can be fed from either PLL_MIPI, or PLL_VIDEO0(2X),
however MIPI DSI output only seems to work when PLL_MIPI is selected and
thus the choice must be hardcoded in.

Currently, this driver can't propagate rate change from N-K-M clocks
(such as PLL_MIPI) upwards. This prevents PLL_VIDEO0 from participating
in setting of the TCON0 data clock rate, limiting the precision with
which a target pixel clock can be matched.

For outputs with fixed TCON0 divider, that is DSI and LVDS, the dotclock
can deviate up to 8% off target.

Signed-off-by: Roman Beranek <me@crly.cz>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Acked-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20230505052110.67514-2-me@crly.cz
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>

diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
index 41519185600a09c4503591dcd1caa1912b8f5f65..eb36f8f77d5540d630c0bbeac773a8bf5efed516 100644 (file)
--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
@@ -528,11 +528,18 @@ static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
                                 0x104, 0, 4, 24, 3, BIT(31),
                                 CLK_SET_RATE_PARENT);
 
+/*
+ * DSI output seems to work only when PLL_MIPI selected. Set it and prevent
+ * the mux from reparenting.
+ */
+#define SUN50I_A64_TCON0_CLK_REG       0x118
+
 static const char * const tcon0_parents[] = { "pll-mipi", "pll-video0-2x" };
 static const u8 tcon0_table[] = { 0, 2, };
 static SUNXI_CCU_MUX_TABLE_WITH_GATE(tcon0_clk, "tcon0", tcon0_parents,
                                     tcon0_table, 0x118, 24, 3, BIT(31),
-                                    CLK_SET_RATE_PARENT);
+                                    CLK_SET_RATE_PARENT |
+                                    CLK_SET_RATE_NO_REPARENT);
 
 static const char * const tcon1_parents[] = { "pll-video0", "pll-video1" };
 static const u8 tcon1_table[] = { 0, 2, };
@@ -953,6 +960,11 @@ static int sun50i_a64_ccu_probe(struct platform_device *pdev)
 
        writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);
 
+       /* Set PLL MIPI as parent for TCON0 */
+       val = readl(reg + SUN50I_A64_TCON0_CLK_REG);
+       val &= ~GENMASK(26, 24);
+       writel(val | (0 << 24), reg + SUN50I_A64_TCON0_CLK_REG);
+
        ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_a64_ccu_desc);
        if (ret)
                return ret;