Merge branch 'arm/dt' into for-next

* arm/dt: (239 commits)
  ARM: mstar: Add mpll to base dtsi
  ARM: mstar: Add the external clocks to the base dsti
  ARM: mstar: Select MSTAR_MSC313_MPLL
  ARM: dts: stm32: Add PTP clock to Ethernet controller
  arm64: dts: mediatek: fix reset GPIO level on pumpkin
  arm64: dts: mt8183: add mt8183 pumpkin board
  dt-bindings: arm64: dts: mediatek: Add mt8183-pumpkin board
  ARM: dts: stm32: Enable crc1 and cryp1 where applicable on DHSOM
  ARM: dts: stm32: Update GPIO line names on PicoITX
  ARM: dts: stm32: Update GPIO line names on DRC02
  ARM: dts: stm32: Fill GPIO line names on AV96
  ARM: dts: stm32: Fill GPIO line names on DHCOM SoM
  dt-bindings: serial: stm32: Use 'type: object' instead of false for 'additionalProperties'
  ARM: stm32: Add a new SoC - STM32H750
  ARM: dts: stm32: add support for art-pi board based on stm32h750xbh6
  ARM: dts: stm32: fix i2c node typo in stm32h743
  ARM: dts: stm32: add new instances for stm32h743 MCU
  ARM: dts: stm32: introduce stm32h7-pinctrl.dtsi to support stm32h750
  dt-bindings: arm: stm32: Add compatible strings for ART-PI board
  Documentation: arm: stm32: Add stm32h750 value line doc
  ...

diff --cc arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
Simple merge

diff --cc arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
index 122c95ddad3053b2c28d6a24bcedad354003bf41,e5d5e6067145a213a4e6cc76926734f5c281849a..984a6b9ded8d7a8c4936f220d099ab2cc755c7c3
--- 1/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
--- 2/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
@@@ -33,9 -33,33 +33,33 @@@
        };
  };
  
+ &eqos {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_eqos>;
+       phy-mode = "rgmii-id";
+       phy-handle = <&ethphy0>;
+       status = "okay";
+ 
+       mdio {
+               compatible = "snps,dwmac-mdio";
+               #address-cells = <1>;
+               #size-cells = <0>;
+ 
+               ethphy0: ethernet-phy@1 {
+                       compatible = "ethernet-phy-ieee802.3-c22";
+                       reg = <0x1>;
+                       ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
+                       ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
+                       ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+                       ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
+                       enet-phy-lane-no-swap;
+               };
+       };
+ };
+ 
  &i2c2 {
        clock-frequency = <400000>;
 -      pinctrl-names = "default";
 +      pinctrl-names = "default", "gpio";
        pinctrl-0 = <&pinctrl_i2c2>;
        pinctrl-1 = <&pinctrl_i2c2_gpio>;
        sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;