u32 tmp;
        int r;
 
-       if (rdev->gart.table.vram.robj == NULL) {
+       if (rdev->gart.robj == NULL) {
                dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
                return -EINVAL;
        }
 void evergreen_pcie_gart_disable(struct radeon_device *rdev)
 {
        u32 tmp;
-       int r;
 
        /* Disable all tables */
        WREG32(VM_CONTEXT0_CNTL, 0);
        WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
        WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
        WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
-       if (rdev->gart.table.vram.robj) {
-               r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
-               if (likely(r == 0)) {
-                       radeon_bo_kunmap(rdev->gart.table.vram.robj);
-                       radeon_bo_unpin(rdev->gart.table.vram.robj);
-                       radeon_bo_unreserve(rdev->gart.table.vram.robj);
-               }
-       }
+       radeon_gart_table_vram_unpin(rdev);
 }
 
 void evergreen_pcie_gart_fini(struct radeon_device *rdev)
 
 {
        int r;
 
-       if (rdev->gart.table.vram.robj == NULL) {
+       if (rdev->gart.robj == NULL) {
                dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
                return -EINVAL;
        }
 
 void cayman_pcie_gart_disable(struct radeon_device *rdev)
 {
-       int r;
-
        /* Disable all tables */
        WREG32(VM_CONTEXT0_CNTL, 0);
        WREG32(VM_CONTEXT1_CNTL, 0);
        WREG32(VM_L2_CNTL2, 0);
        WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
               L2_CACHE_BIGK_FRAGMENT_SIZE(6));
-       if (rdev->gart.table.vram.robj) {
-               r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
-               if (likely(r == 0)) {
-                       radeon_bo_kunmap(rdev->gart.table.vram.robj);
-                       radeon_bo_unpin(rdev->gart.table.vram.robj);
-                       radeon_bo_unreserve(rdev->gart.table.vram.robj);
-               }
-       }
+       radeon_gart_table_vram_unpin(rdev);
 }
 
 void cayman_pcie_gart_fini(struct radeon_device *rdev)
 
 {
        int r;
 
-       if (rdev->gart.table.ram.ptr) {
+       if (rdev->gart.ptr) {
                WARN(1, "R100 PCI GART already initialized\n");
                return 0;
        }
 
 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
 {
+       u32 *gtt = rdev->gart.ptr;
+
        if (i < 0 || i > rdev->gart.num_gpu_pages) {
                return -EINVAL;
        }
-       rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
+       gtt[i] = cpu_to_le32(lower_32_bits(addr));
        return 0;
 }
 
 
 
 int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
 {
-       void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
+       void __iomem *ptr = rdev->gart.ptr;
 
        if (i < 0 || i > rdev->gart.num_gpu_pages) {
                return -EINVAL;
 {
        int r;
 
-       if (rdev->gart.table.vram.robj) {
+       if (rdev->gart.robj) {
                WARN(1, "RV370 PCIE GART already initialized\n");
                return 0;
        }
        uint32_t tmp;
        int r;
 
-       if (rdev->gart.table.vram.robj == NULL) {
+       if (rdev->gart.robj == NULL) {
                dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
                return -EINVAL;
        }
 void rv370_pcie_gart_disable(struct radeon_device *rdev)
 {
        u32 tmp;
-       int r;
 
        WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, 0);
        WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, 0);
        tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
        tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
        WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
-       if (rdev->gart.table.vram.robj) {
-               r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
-               if (likely(r == 0)) {
-                       radeon_bo_kunmap(rdev->gart.table.vram.robj);
-                       radeon_bo_unpin(rdev->gart.table.vram.robj);
-                       radeon_bo_unreserve(rdev->gart.table.vram.robj);
-               }
-       }
+       radeon_gart_table_vram_unpin(rdev);
 }
 
 void rv370_pcie_gart_fini(struct radeon_device *rdev)
 
        /* flush hdp cache so updates hit vram */
        if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
            !(rdev->flags & RADEON_IS_AGP)) {
-               void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
+               void __iomem *ptr = (void *)rdev->gart.ptr;
                u32 tmp;
 
                /* r7xx hw bug.  write to HDP_DEBUG1 followed by fb read
 {
        int r;
 
-       if (rdev->gart.table.vram.robj) {
+       if (rdev->gart.robj) {
                WARN(1, "R600 PCIE GART already initialized\n");
                return 0;
        }
        u32 tmp;
        int r, i;
 
-       if (rdev->gart.table.vram.robj == NULL) {
+       if (rdev->gart.robj == NULL) {
                dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
                return -EINVAL;
        }
 void r600_pcie_gart_disable(struct radeon_device *rdev)
 {
        u32 tmp;
-       int i, r;
+       int i;
 
        /* Disable all tables */
        for (i = 0; i < 7; i++)
        WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
        WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
        WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
-       if (rdev->gart.table.vram.robj) {
-               r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
-               if (likely(r == 0)) {
-                       radeon_bo_kunmap(rdev->gart.table.vram.robj);
-                       radeon_bo_unpin(rdev->gart.table.vram.robj);
-                       radeon_bo_unreserve(rdev->gart.table.vram.robj);
-               }
-       }
+       radeon_gart_table_vram_unpin(rdev);
 }
 
 void r600_pcie_gart_fini(struct radeon_device *rdev)
 
  */
 struct radeon_mc;
 
-struct radeon_gart_table_ram {
-       volatile uint32_t               *ptr;
-};
-
-struct radeon_gart_table_vram {
-       struct radeon_bo                *robj;
-       volatile uint32_t               *ptr;
-};
-
-union radeon_gart_table {
-       struct radeon_gart_table_ram    ram;
-       struct radeon_gart_table_vram   vram;
-};
-
 #define RADEON_GPU_PAGE_SIZE 4096
 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
 #define RADEON_GPU_PAGE_SHIFT 12
 
 struct radeon_gart {
        dma_addr_t                      table_addr;
+       struct radeon_bo                *robj;
+       void                            *ptr;
        unsigned                        num_gpu_pages;
        unsigned                        num_cpu_pages;
        unsigned                        table_size;
-       union radeon_gart_table         table;
        struct page                     **pages;
        dma_addr_t                      *pages_addr;
        bool                            *ttm_alloced;
 void radeon_gart_table_ram_free(struct radeon_device *rdev);
 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
 void radeon_gart_table_vram_free(struct radeon_device *rdev);
+int radeon_gart_table_vram_pin(struct radeon_device *rdev);
+void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
 int radeon_gart_init(struct radeon_device *rdev);
 void radeon_gart_fini(struct radeon_device *rdev);
 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
                     int pages, struct page **pagelist,
                     dma_addr_t *dma_addr);
+void radeon_gart_restore(struct radeon_device *rdev);
 
 
 /*
 /* AGP */
 extern int radeon_gpu_reset(struct radeon_device *rdev);
 extern void radeon_agp_disable(struct radeon_device *rdev);
-extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
-extern void radeon_gart_restore(struct radeon_device *rdev);
 extern int radeon_modeset_init(struct radeon_device *rdev);
 extern void radeon_modeset_fini(struct radeon_device *rdev);
 extern bool radeon_card_posted(struct radeon_device *rdev);
 
                              rdev->gart.table_size >> PAGE_SHIFT);
        }
 #endif
-       rdev->gart.table.ram.ptr = ptr;
-       memset((void *)rdev->gart.table.ram.ptr, 0, rdev->gart.table_size);
+       rdev->gart.ptr = ptr;
+       memset((void *)rdev->gart.ptr, 0, rdev->gart.table_size);
        return 0;
 }
 
 void radeon_gart_table_ram_free(struct radeon_device *rdev)
 {
-       if (rdev->gart.table.ram.ptr == NULL) {
+       if (rdev->gart.ptr == NULL) {
                return;
        }
 #ifdef CONFIG_X86
        if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480 ||
            rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
-               set_memory_wb((unsigned long)rdev->gart.table.ram.ptr,
+               set_memory_wb((unsigned long)rdev->gart.ptr,
                              rdev->gart.table_size >> PAGE_SHIFT);
        }
 #endif
        pci_free_consistent(rdev->pdev, rdev->gart.table_size,
-                           (void *)rdev->gart.table.ram.ptr,
+                           (void *)rdev->gart.ptr,
                            rdev->gart.table_addr);
-       rdev->gart.table.ram.ptr = NULL;
+       rdev->gart.ptr = NULL;
        rdev->gart.table_addr = 0;
 }
 
 {
        int r;
 
-       if (rdev->gart.table.vram.robj == NULL) {
+       if (rdev->gart.robj == NULL) {
                r = radeon_bo_create(rdev, rdev->gart.table_size,
                                     PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
-                                    &rdev->gart.table.vram.robj);
+                                    &rdev->gart.robj);
                if (r) {
                        return r;
                }
        uint64_t gpu_addr;
        int r;
 
-       r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
+       r = radeon_bo_reserve(rdev->gart.robj, false);
        if (unlikely(r != 0))
                return r;
-       r = radeon_bo_pin(rdev->gart.table.vram.robj,
+       r = radeon_bo_pin(rdev->gart.robj,
                                RADEON_GEM_DOMAIN_VRAM, &gpu_addr);
        if (r) {
-               radeon_bo_unreserve(rdev->gart.table.vram.robj);
+               radeon_bo_unreserve(rdev->gart.robj);
                return r;
        }
-       r = radeon_bo_kmap(rdev->gart.table.vram.robj,
-                               (void **)&rdev->gart.table.vram.ptr);
+       r = radeon_bo_kmap(rdev->gart.robj, &rdev->gart.ptr);
        if (r)
-               radeon_bo_unpin(rdev->gart.table.vram.robj);
-       radeon_bo_unreserve(rdev->gart.table.vram.robj);
+               radeon_bo_unpin(rdev->gart.robj);
+       radeon_bo_unreserve(rdev->gart.robj);
        rdev->gart.table_addr = gpu_addr;
        return r;
 }
 
-void radeon_gart_table_vram_free(struct radeon_device *rdev)
+void radeon_gart_table_vram_unpin(struct radeon_device *rdev)
 {
        int r;
 
-       if (rdev->gart.table.vram.robj == NULL) {
+       if (rdev->gart.robj == NULL) {
                return;
        }
-       r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
+       r = radeon_bo_reserve(rdev->gart.robj, false);
        if (likely(r == 0)) {
-               radeon_bo_kunmap(rdev->gart.table.vram.robj);
-               radeon_bo_unpin(rdev->gart.table.vram.robj);
-               radeon_bo_unreserve(rdev->gart.table.vram.robj);
+               radeon_bo_kunmap(rdev->gart.robj);
+               radeon_bo_unpin(rdev->gart.robj);
+               radeon_bo_unreserve(rdev->gart.robj);
+               rdev->gart.ptr = NULL;
        }
-       radeon_bo_unref(&rdev->gart.table.vram.robj);
+}
+
+void radeon_gart_table_vram_free(struct radeon_device *rdev)
+{
+       if (rdev->gart.robj == NULL) {
+               return;
+       }
+       radeon_gart_table_vram_unpin(rdev);
+       radeon_bo_unref(&rdev->gart.robj);
 }
 
 
                if (rdev->gart.pages[p]) {
                        if (!rdev->gart.ttm_alloced[p])
                                pci_unmap_page(rdev->pdev, rdev->gart.pages_addr[p],
-                                               PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
+                                               PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
                        rdev->gart.pages[p] = NULL;
                        rdev->gart.pages_addr[p] = rdev->dummy_page.addr;
                        page_base = rdev->gart.pages_addr[p];
                        for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
-                               radeon_gart_set_page(rdev, t, page_base);
+                               if (rdev->gart.ptr) {
+                                       radeon_gart_set_page(rdev, t, page_base);
+                               }
                                page_base += RADEON_GPU_PAGE_SIZE;
                        }
                }
                        }
                }
                rdev->gart.pages[p] = pagelist[i];
-               page_base = rdev->gart.pages_addr[p];
-               for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
-                       radeon_gart_set_page(rdev, t, page_base);
-                       page_base += RADEON_GPU_PAGE_SIZE;
+               if (rdev->gart.ptr) {
+                       page_base = rdev->gart.pages_addr[p];
+                       for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
+                               radeon_gart_set_page(rdev, t, page_base);
+                               page_base += RADEON_GPU_PAGE_SIZE;
+                       }
                }
        }
        mb();
        int i, j, t;
        u64 page_base;
 
+       if (!rdev->gart.ptr) {
+               return;
+       }
        for (i = 0, t = 0; i < rdev->gart.num_cpu_pages; i++) {
                page_base = rdev->gart.pages_addr[i];
                for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
 
 {
        int r;
 
-       if (rdev->gart.table.ram.ptr) {
+       if (rdev->gart.ptr) {
                WARN(1, "RS400 GART already initialized\n");
                return 0;
        }
 int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
 {
        uint32_t entry;
+       u32 *gtt = rdev->gart.ptr;
 
        if (i < 0 || i > rdev->gart.num_gpu_pages) {
                return -EINVAL;
                ((upper_32_bits(addr) & 0xff) << 4) |
                RS400_PTE_WRITEABLE | RS400_PTE_READABLE;
        entry = cpu_to_le32(entry);
-       rdev->gart.table.ram.ptr[i] = entry;
+       gtt[i] = entry;
        return 0;
 }
 
 
 {
        int r;
 
-       if (rdev->gart.table.vram.robj) {
+       if (rdev->gart.robj) {
                WARN(1, "RS600 GART already initialized\n");
                return 0;
        }
        u32 tmp;
        int r, i;
 
-       if (rdev->gart.table.vram.robj == NULL) {
+       if (rdev->gart.robj == NULL) {
                dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
                return -EINVAL;
        }
 void rs600_gart_disable(struct radeon_device *rdev)
 {
        u32 tmp;
-       int r;
 
        /* FIXME: disable out of gart access */
        WREG32_MC(R_000100_MC_PT0_CNTL, 0);
        tmp = RREG32_MC(R_000009_MC_CNTL1);
        WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);
-       if (rdev->gart.table.vram.robj) {
-               r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
-               if (r == 0) {
-                       radeon_bo_kunmap(rdev->gart.table.vram.robj);
-                       radeon_bo_unpin(rdev->gart.table.vram.robj);
-                       radeon_bo_unreserve(rdev->gart.table.vram.robj);
-               }
-       }
+       radeon_gart_table_vram_unpin(rdev);
 }
 
 void rs600_gart_fini(struct radeon_device *rdev)
 
 int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
 {
-       void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
+       void __iomem *ptr = (void *)rdev->gart.ptr;
 
        if (i < 0 || i > rdev->gart.num_gpu_pages) {
                return -EINVAL;
 
        u32 tmp;
        int r, i;
 
-       if (rdev->gart.table.vram.robj == NULL) {
+       if (rdev->gart.robj == NULL) {
                dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
                return -EINVAL;
        }
 void rv770_pcie_gart_disable(struct radeon_device *rdev)
 {
        u32 tmp;
-       int i, r;
+       int i;
 
        /* Disable all tables */
        for (i = 0; i < 7; i++)
        WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
        WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
        WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
-       if (rdev->gart.table.vram.robj) {
-               r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
-               if (likely(r == 0)) {
-                       radeon_bo_kunmap(rdev->gart.table.vram.robj);
-                       radeon_bo_unpin(rdev->gart.table.vram.robj);
-                       radeon_bo_unreserve(rdev->gart.table.vram.robj);
-               }
-       }
+       radeon_gart_table_vram_unpin(rdev);
 }
 
 void rv770_pcie_gart_fini(struct radeon_device *rdev)