perf: Extend the bit width of the arch-specific flag

The auto counter reload feature requires an event flag to indicate an
auto counter reload group, which can only be scheduled on specific
counters that enumerated in CPUID. However, the hw_perf_event.flags has
run out on X86.

Two solutions were considered to address the issue.
- Currently, 20 bits are reserved for the architecture-specific flags.
  Only the bit 31 is used for the generic flag. There is still plenty
  of space left. Reserve 8 more bits for the arch-specific flags.
- Add a new X86 specific hw_perf_event.flags1 to support more flags.

The former is implemented. Enough room is still left in the global
generic flag.

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Tested-by: Thomas Falcon <thomas.falcon@intel.com>
Link: https://lkml.kernel.org/r/20250327195217.2683619-4-kan.liang@linux.intel.com

diff --git a/arch/x86/events/perf_event_flags.h b/arch/x86/events/perf_event_flags.h
index 1d9e385649b5733ddf800e60c0aa9dc8969dc0a8..70078334e4a33820a0b57c58c8cdd1d62c4fe0ad 100644 (file)
--- a/arch/x86/events/perf_event_flags.h
+++ b/arch/x86/events/perf_event_flags.h
@@ -2,23 +2,24 @@
 /*
  * struct hw_perf_event.flags flags
  */
-PERF_ARCH(PEBS_LDLAT,          0x00001) /* ld+ldlat data address sampling */
-PERF_ARCH(PEBS_ST,             0x00002) /* st data address sampling */
-PERF_ARCH(PEBS_ST_HSW,         0x00004) /* haswell style datala, store */
-PERF_ARCH(PEBS_LD_HSW,         0x00008) /* haswell style datala, load */
-PERF_ARCH(PEBS_NA_HSW,         0x00010) /* haswell style datala, unknown */
-PERF_ARCH(EXCL,                        0x00020) /* HT exclusivity on counter */
-PERF_ARCH(DYNAMIC,             0x00040) /* dynamic alloc'd constraint */
-PERF_ARCH(PEBS_CNTR,           0x00080) /* PEBS counters snapshot */
-PERF_ARCH(EXCL_ACCT,           0x00100) /* accounted EXCL event */
-PERF_ARCH(AUTO_RELOAD,         0x00200) /* use PEBS auto-reload */
-PERF_ARCH(LARGE_PEBS,          0x00400) /* use large PEBS */
-PERF_ARCH(PEBS_VIA_PT,         0x00800) /* use PT buffer for PEBS */
-PERF_ARCH(PAIR,                        0x01000) /* Large Increment per Cycle */
-PERF_ARCH(LBR_SELECT,          0x02000) /* Save/Restore MSR_LBR_SELECT */
-PERF_ARCH(TOPDOWN,             0x04000) /* Count Topdown slots/metrics events */
-PERF_ARCH(PEBS_STLAT,          0x08000) /* st+stlat data address sampling */
-PERF_ARCH(AMD_BRS,             0x10000) /* AMD Branch Sampling */
-PERF_ARCH(PEBS_LAT_HYBRID,     0x20000) /* ld and st lat for hybrid */
-PERF_ARCH(NEEDS_BRANCH_STACK,  0x40000) /* require branch stack setup */
-PERF_ARCH(BRANCH_COUNTERS,     0x80000) /* logs the counters in the extra space of each branch */
+PERF_ARCH(PEBS_LDLAT,          0x0000001) /* ld+ldlat data address sampling */
+PERF_ARCH(PEBS_ST,             0x0000002) /* st data address sampling */
+PERF_ARCH(PEBS_ST_HSW,         0x0000004) /* haswell style datala, store */
+PERF_ARCH(PEBS_LD_HSW,         0x0000008) /* haswell style datala, load */
+PERF_ARCH(PEBS_NA_HSW,         0x0000010) /* haswell style datala, unknown */
+PERF_ARCH(EXCL,                        0x0000020) /* HT exclusivity on counter */
+PERF_ARCH(DYNAMIC,             0x0000040) /* dynamic alloc'd constraint */
+PERF_ARCH(PEBS_CNTR,           0x0000080) /* PEBS counters snapshot */
+PERF_ARCH(EXCL_ACCT,           0x0000100) /* accounted EXCL event */
+PERF_ARCH(AUTO_RELOAD,         0x0000200) /* use PEBS auto-reload */
+PERF_ARCH(LARGE_PEBS,          0x0000400) /* use large PEBS */
+PERF_ARCH(PEBS_VIA_PT,         0x0000800) /* use PT buffer for PEBS */
+PERF_ARCH(PAIR,                        0x0001000) /* Large Increment per Cycle */
+PERF_ARCH(LBR_SELECT,          0x0002000) /* Save/Restore MSR_LBR_SELECT */
+PERF_ARCH(TOPDOWN,             0x0004000) /* Count Topdown slots/metrics events */
+PERF_ARCH(PEBS_STLAT,          0x0008000) /* st+stlat data address sampling */
+PERF_ARCH(AMD_BRS,             0x0010000) /* AMD Branch Sampling */
+PERF_ARCH(PEBS_LAT_HYBRID,     0x0020000) /* ld and st lat for hybrid */
+PERF_ARCH(NEEDS_BRANCH_STACK,  0x0040000) /* require branch stack setup */
+PERF_ARCH(BRANCH_COUNTERS,     0x0080000) /* logs the counters in the extra space of each branch */
+PERF_ARCH(ACR,                 0x0100000) /* Auto counter reload */

diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h
index 54dad174ed7a0213959328927cc7c240f6fcdc0f..5c547329cf02482357e9b6314d8abd323e68fd29 100644 (file)
--- a/include/linux/perf_event.h
+++ b/include/linux/perf_event.h
@@ -144,7 +144,7 @@ struct hw_perf_event_extra {
  * PERF_EVENT_FLAG_ARCH bits are reserved for architecture-specific
  * usage.
  */
-#define PERF_EVENT_FLAG_ARCH                   0x000fffff
+#define PERF_EVENT_FLAG_ARCH                   0x0fffffff
 #define PERF_EVENT_FLAG_USER_READ_CNT          0x80000000
 
 static_assert((PERF_EVENT_FLAG_USER_READ_CNT & PERF_EVENT_FLAG_ARCH) == 0);