drm/i915: Program VLV/CHV PIPE_MSA_MISC register

VLV/CHV have an extra register to configure some stereo3d
signalling details via DP MSA. Make sure we reset that
register to zero (since we don't do any stereo3d stuff).

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230314130255.23273-5-ville.syrjala@linux.intel.com
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 8b009eb7c1da6bf74f608074d53651c19664b1ce..b8691bcdf4092cb2acc7fa5b6695bd355671e045 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2139,6 +2139,8 @@ static void valleyview_crtc_enable(struct intel_atomic_state *state,
 
        intel_set_pipe_src_size(new_crtc_state);
 
+       intel_de_write(dev_priv, VLV_PIPE_MSA_MISC(pipe), 0);
+
        if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
                intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY);
                intel_de_write(dev_priv, CHV_CANVAS(pipe), 0);

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index dbed3d1d0c5d210f9e7ec8f96f6fcd1f0a25ba96..46e5c459d64e74be688859601b6860b638d3888d 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7574,6 +7574,12 @@ enum skl_power_gate {
 #define PIPE_FLIPDONETIMSTMP(pipe)     \
        _MMIO_PIPE(pipe, _PIPE_FLIPDONETMSTMP_A, _PIPE_FLIPDONETMSTMP_B)
 
+#define _VLV_PIPE_MSA_MISC_A                   0x70048
+#define VLV_PIPE_MSA_MISC(pipe)                \
+                       _MMIO_PIPE2(pipe, _VLV_PIPE_MSA_MISC_A)
+#define   VLV_MSA_MISC1_HW_ENABLE                      REG_BIT(31)
+#define   VLV_MSA_MISC1_SW_S3D_MASK                    REG_GENMASK(2, 0) /* MSA MISC1 3:1 */
+
 #define GGC                            _MMIO(0x108040)
 #define   GMS_MASK                     REG_GENMASK(15, 8)
 #define   GGMS_MASK                    REG_GENMASK(7, 6)