#define assert(expr)
 #endif
 
-#ifdef TRUE
-#undef TRUE
-#endif
-#ifdef FALSE
-#undef FALSE
-#endif
-#define TRUE  1
-#define FALSE 0
-
 #define MB_ (1024*1024)
 #define KB_ (1024)
 
        char *name;             /* ASCII name of chipset */
        long maxclock[5];               /* maximum video clock */
        /* for  1/4bpp, 8bpp 15/16bpp, 24bpp, 32bpp - numbers from xorg code */
-       unsigned init_sr07 : 1; /* init SR07 during init_vgachip() */
-       unsigned init_sr1f : 1; /* write SR1F during init_vgachip() */
-       unsigned scrn_start_bit19 : 1; /* construct bit 19 of screen start address */
+       bool init_sr07 : 1; /* init SR07 during init_vgachip() */
+       bool init_sr1f : 1; /* write SR1F during init_vgachip() */
+       bool scrn_start_bit19 : 1; /* construct bit 19 of screen start address */
 
        /* initial SR07 value, then for each mode */
        unsigned char sr07;
                        /* the SD64/P4 have a higher max. videoclock */
                        140000, 140000, 140000, 140000, 140000,
                },
-               .init_sr07              = TRUE,
-               .init_sr1f              = TRUE,
-               .scrn_start_bit19       = TRUE,
+               .init_sr07              = true,
+               .init_sr1f              = true,
+               .scrn_start_bit19       = true,
                .sr07                   = 0xF0,
                .sr07_1bpp              = 0xF0,
                .sr07_8bpp              = 0xF1,
                        /* guess */
                        90000, 90000, 90000, 90000, 90000
                },
-               .init_sr07              = TRUE,
-               .init_sr1f              = TRUE,
-               .scrn_start_bit19       = FALSE,
+               .init_sr07              = true,
+               .init_sr1f              = true,
+               .scrn_start_bit19       = false,
                .sr07                   = 0x80,
                .sr07_1bpp              = 0x80,
                .sr07_8bpp              = 0x81,
                        /* guess */
                        90000, 90000, 90000, 90000, 90000
                },
-               .init_sr07              = TRUE,
-               .init_sr1f              = TRUE,
-               .scrn_start_bit19       = FALSE,
+               .init_sr07              = true,
+               .init_sr1f              = true,
+               .scrn_start_bit19       = false,
                .sr07                   = 0x20,
                .sr07_1bpp              = 0x20,
                .sr07_8bpp              = 0x21,
                        /* guess */
                        90000, 90000, 90000, 90000, 90000
                },
-               .init_sr07              = TRUE,
-               .init_sr1f              = TRUE,
-               .scrn_start_bit19       = FALSE,
+               .init_sr07              = true,
+               .init_sr1f              = true,
+               .scrn_start_bit19       = false,
                .sr07                   = 0x80,
                .sr07_1bpp              = 0x80,
                .sr07_8bpp              = 0x81,
                .maxclock               = {
                        135100, 135100, 85500, 85500, 0
                },
-               .init_sr07              = TRUE,
-               .init_sr1f              = FALSE,
-               .scrn_start_bit19       = TRUE,
+               .init_sr07              = true,
+               .init_sr1f              = false,
+               .scrn_start_bit19       = true,
                .sr07                   = 0x20,
                .sr07_1bpp              = 0x20,
                .sr07_8bpp              = 0x21,
                        /* for the GD5430.  GD5446 can do more... */
                        85500, 85500, 50000, 28500, 0
                },
-               .init_sr07              = TRUE,
-               .init_sr1f              = TRUE,
-               .scrn_start_bit19       = TRUE,
+               .init_sr07              = true,
+               .init_sr1f              = true,
+               .scrn_start_bit19       = true,
                .sr07                   = 0xA0,
                .sr07_1bpp              = 0xA1,
                .sr07_1bpp_mux          = 0xA7,
                .maxclock               = {
                        135100, 200000, 200000, 135100, 135100
                },
-               .init_sr07              = TRUE,
-               .init_sr1f              = TRUE,
-               .scrn_start_bit19       = TRUE,
+               .init_sr07              = true,
+               .init_sr1f              = true,
+               .scrn_start_bit19       = true,
                .sr07                   = 0x10,
                .sr07_1bpp              = 0x11,
                .sr07_8bpp              = 0x11,
                        /* guess */
                        135100, 135100, 135100, 135100, 135100,
                },
-               .init_sr07              = FALSE,
-               .init_sr1f              = FALSE,
-               .scrn_start_bit19       = TRUE,
+               .init_sr07              = false,
+               .init_sr1f              = false,
+               .scrn_start_bit19       = true,
        }
 };
 
 
        default:
                DPRINTK("Unsupported bpp size: %d\n", var->bits_per_pixel);
-               assert (FALSE);
+               assert(false);
                /* should never occur */
                break;
        }
 
        default:
                DPRINTK("Unsupported bpp size: %d\n", var->bits_per_pixel);
-               assert (FALSE);
+               assert(false);
                /* should never occur */
                break;
        }
                        break;
                default:
                        /* should never occur */
-                       assert (FALSE);
+                       assert(false);
                        break;
                }