};
  
                mmc0: mmc@01c0f000 {
 -                      compatible = "allwinner,sun5i-a13-mmc";
 +                      compatible = "allwinner,sun7i-a20-mmc";
                        reg = <0x01c0f000 0x1000>;
-                       clocks = <&ahb1_gates 8>,
-                                <&mmc0_clk 0>,
-                                <&mmc0_clk 1>,
-                                <&mmc0_clk 2>;
+                       clocks = <&ccu CLK_AHB1_MMC0>,
+                                <&ccu CLK_MMC0>,
+                                <&ccu CLK_MMC0_OUTPUT>,
+                                <&ccu CLK_MMC0_SAMPLE>;
                        clock-names = "ahb",
                                      "mmc",
                                      "output",
                };
  
                mmc1: mmc@01c10000 {
 -                      compatible = "allwinner,sun5i-a13-mmc";
 +                      compatible = "allwinner,sun7i-a20-mmc";
                        reg = <0x01c10000 0x1000>;
-                       clocks = <&ahb1_gates 9>,
-                                <&mmc1_clk 0>,
-                                <&mmc1_clk 1>,
-                                <&mmc1_clk 2>;
+                       clocks = <&ccu CLK_AHB1_MMC1>,
+                                <&ccu CLK_MMC1>,
+                                <&ccu CLK_MMC1_OUTPUT>,
+                                <&ccu CLK_MMC1_SAMPLE>;
                        clock-names = "ahb",
                                      "mmc",
                                      "output",
                };
  
                mmc2: mmc@01c11000 {
 -                      compatible = "allwinner,sun5i-a13-mmc";
 +                      compatible = "allwinner,sun7i-a20-mmc";
                        reg = <0x01c11000 0x1000>;
-                       clocks = <&ahb1_gates 10>,
-                                <&mmc2_clk 0>,
-                                <&mmc2_clk 1>,
-                                <&mmc2_clk 2>;
+                       clocks = <&ccu CLK_AHB1_MMC2>,
+                                <&ccu CLK_MMC2>,
+                                <&ccu CLK_MMC2_OUTPUT>,
+                                <&ccu CLK_MMC2_SAMPLE>;
                        clock-names = "ahb",
                                      "mmc",
                                      "output",
                };
  
                mmc3: mmc@01c12000 {
 -                      compatible = "allwinner,sun5i-a13-mmc";
 +                      compatible = "allwinner,sun7i-a20-mmc";
                        reg = <0x01c12000 0x1000>;
-                       clocks = <&ahb1_gates 11>,
-                                <&mmc3_clk 0>,
-                                <&mmc3_clk 1>,
-                                <&mmc3_clk 2>;
+                       clocks = <&ccu CLK_AHB1_MMC3>,
+                                <&ccu CLK_MMC3>,
+                                <&ccu CLK_MMC3_OUTPUT>,
+                                <&ccu CLK_MMC3_SAMPLE>;
                        clock-names = "ahb",
                                      "mmc",
                                      "output",
 
                };
  
                mmc0: mmc@01c0f000 {
 -                      compatible = "allwinner,sun5i-a13-mmc";
 +                      compatible = "allwinner,sun7i-a20-mmc";
                        reg = <0x01c0f000 0x1000>;
-                       clocks = <&ahb1_gates 8>,
-                                <&mmc0_clk 0>,
-                                <&mmc0_clk 1>,
-                                <&mmc0_clk 2>;
+                       clocks = <&ccu CLK_BUS_MMC0>,
+                                <&ccu CLK_MMC0>,
+                                <&ccu CLK_MMC0_OUTPUT>,
+                                <&ccu CLK_MMC0_SAMPLE>;
                        clock-names = "ahb",
                                      "mmc",
                                      "output",
                };
  
                mmc1: mmc@01c10000 {
 -                      compatible = "allwinner,sun5i-a13-mmc";
 +                      compatible = "allwinner,sun7i-a20-mmc";
                        reg = <0x01c10000 0x1000>;
-                       clocks = <&ahb1_gates 9>,
-                                <&mmc1_clk 0>,
-                                <&mmc1_clk 1>,
-                                <&mmc1_clk 2>;
+                       clocks = <&ccu CLK_BUS_MMC1>,
+                                <&ccu CLK_MMC1>,
+                                <&ccu CLK_MMC1_OUTPUT>,
+                                <&ccu CLK_MMC1_SAMPLE>;
                        clock-names = "ahb",
                                      "mmc",
                                      "output",
                };
  
                mmc2: mmc@01c11000 {
 -                      compatible = "allwinner,sun5i-a13-mmc";
 +                      compatible = "allwinner,sun7i-a20-mmc";
                        reg = <0x01c11000 0x1000>;
-                       clocks = <&ahb1_gates 10>,
-                                <&mmc2_clk 0>,
-                                <&mmc2_clk 1>,
-                                <&mmc2_clk 2>;
+                       clocks = <&ccu CLK_BUS_MMC2>,
+                                <&ccu CLK_MMC2>,
+                                <&ccu CLK_MMC2_OUTPUT>,
+                                <&ccu CLK_MMC2_SAMPLE>;
                        clock-names = "ahb",
                                      "mmc",
                                      "output",