ARM: dts: qcom: msm8974: add clocks and clock-names to mmcc device

Add clocks and clock-names nodes to the mmcc device to bind clocks using
the DT links.

Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221204124508.1415713-12-dmitry.baryshkov@linaro.org

diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index b53d4f91ebdbb400f1ac7dd56eada248f384a157..db21d2135baf72d54e4b647250254113248679e5 100644 (file)
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -1528,6 +1528,30 @@
                        #reset-cells = <1>;
                        #power-domain-cells = <1>;
                        reg = <0xfd8c0000 0x6000>;
+                       clocks = <&xo_board>,
+                                <&gcc GCC_MMSS_GPLL0_CLK_SRC>,
+                                <&gcc GPLL0_VOTE>,
+                                <&gcc GPLL1_VOTE>,
+                                <&rpmcc RPM_SMD_GFX3D_CLK_SRC>,
+                                <&dsi0_phy 1>,
+                                <&dsi0_phy 0>,
+                                <&dsi1_phy 1>,
+                                <&dsi1_phy 0>,
+                                <0>,
+                                <0>,
+                                <0>;
+                       clock-names = "xo",
+                                     "mmss_gpll0_vote",
+                                     "gpll0_vote",
+                                     "gpll1_vote",
+                                     "gfx3d_clk_src",
+                                     "dsi0pll",
+                                     "dsi0pllbyte",
+                                     "dsi1pll",
+                                     "dsi1pllbyte",
+                                     "hdmipll",
+                                     "edp_link_clk",
+                                     "edp_vco_div";
                };
 
                mdss: mdss@fd900000 {