perf/x86: Support Retire Latency

Retire Latency reports the number of elapsed core clocks between the
retirement of the instruction indicated by the Instruction Pointer field
of the PEBS record and the retirement of the prior instruction. It's
enumerated by the IA32_PERF_CAPABILITIES.PEBS_TIMING_INFO[17].

Add flag PMU_FL_RETIRE_LATENCY to indicate the availability of the
feature.

The Retire Latency is not supported by the fixed counter 0 on p-core of
MTL.

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Acked-by: Peter Zijlstra <peterz@infradead.org>
Link: https://lore.kernel.org/r/20230104201349.1451191-3-kan.liang@linux.intel.com

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index d2030be04e4a11033e8e135229353accb30af00f..a5678ab6d3e35c6e9f2dd7848ce2cbb00e78147c 100644 (file)
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -4210,6 +4210,9 @@ static struct event_constraint fixed0_counter0_constraint =
 static struct event_constraint fixed0_counter0_1_constraint =
                        INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000003ULL);
 
+static struct event_constraint counters_1_7_constraint =
+                       INTEL_ALL_EVENT_CONSTRAINT(0, 0xfeULL);
+
 static struct event_constraint *
 hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
                          struct perf_event *event)
@@ -4374,6 +4377,30 @@ cmt_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
        return c;
 }
 
+static struct event_constraint *
+rwc_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
+                         struct perf_event *event)
+{
+       struct event_constraint *c;
+
+       c = spr_get_event_constraints(cpuc, idx, event);
+
+       /* The Retire Latency is not supported by the fixed counter 0. */
+       if (event->attr.precise_ip &&
+           (event->attr.sample_type & PERF_SAMPLE_WEIGHT_TYPE) &&
+           constraint_match(&fixed0_constraint, event->hw.config)) {
+               /*
+                * The Instruction PDIR is only available
+                * on the fixed counter 0. Error out for this case.
+                */
+               if (event->attr.precise_ip == 3)
+                       return &emptyconstraint;
+               return &counters_1_7_constraint;
+       }
+
+       return c;
+}
+
 static struct event_constraint *
 mtl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
                          struct perf_event *event)
@@ -4381,7 +4408,7 @@ mtl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
        struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
 
        if (pmu->cpu_type == hybrid_big)
-               return spr_get_event_constraints(cpuc, idx, event);
+               return rwc_get_event_constraints(cpuc, idx, event);
        if (pmu->cpu_type == hybrid_small)
                return cmt_get_event_constraints(cpuc, idx, event);
 
@@ -6718,6 +6745,9 @@ __init int intel_pmu_init(void)
        if (is_hybrid())
                intel_pmu_check_hybrid_pmus((u64)fixed_mask);
 
+       if (x86_pmu.intel_cap.pebs_timing_info)
+               x86_pmu.flags |= PMU_FL_RETIRE_LATENCY;
+
        intel_aux_output_init();
 
        return 0;

diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index e991c54916d1348d6db42c225d2f8b7aa280d826..6ec326b47e2edeccb6e3cf5037c2b00d8c2dd876 100644 (file)
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -1753,6 +1753,7 @@ static void adaptive_pebs_save_regs(struct pt_regs *regs,
 
 #define PEBS_LATENCY_MASK                      0xffff
 #define PEBS_CACHE_LATENCY_OFFSET              32
+#define PEBS_RETIRE_LATENCY_OFFSET             32
 
 /*
  * With adaptive PEBS the layout depends on what fields are configured.
@@ -1804,6 +1805,9 @@ static void setup_pebs_adaptive_sample_data(struct perf_event *event,
        set_linear_ip(regs, basic->ip);
        regs->flags = PERF_EFLAGS_EXACT;
 
+       if ((sample_type & PERF_SAMPLE_WEIGHT_STRUCT) && (x86_pmu.flags & PMU_FL_RETIRE_LATENCY))
+               data->weight.var3_w = format_size >> PEBS_RETIRE_LATENCY_OFFSET & PEBS_LATENCY_MASK;
+
        /*
         * The record for MEMINFO is in front of GP
         * But PERF_SAMPLE_TRANSACTION needs gprs->ax.

diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index 1ac9d9e3c55c172c79474ca39622335f30e4c959..d6de4487348cb3fa2081a60febf454488b14a19b 100644 (file)
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -608,6 +608,7 @@ union perf_capabilities {
                u64     pebs_baseline:1;
                u64     perf_metrics:1;
                u64     pebs_output_pt_available:1;
+               u64     pebs_timing_info:1;
                u64     anythread_deprecated:1;
        };
        u64     capabilities;
@@ -1003,6 +1004,7 @@ do {                                                                      \
 #define PMU_FL_PAIR            0x40 /* merge counters for large incr. events */
 #define PMU_FL_INSTR_LATENCY   0x80 /* Support Instruction Latency in PEBS Memory Info Record */
 #define PMU_FL_MEM_LOADS_AUX   0x100 /* Require an auxiliary event for the complete memory info */
+#define PMU_FL_RETIRE_LATENCY  0x200 /* Support Retire Latency in PEBS */
 
 #define EVENT_VAR(_id)  event_attr_##_id
 #define EVENT_PTR(_id) &event_attr_##_id.attr.attr