riscv/barrier: Consolidate fence definitions

Disparate fence implementations are consolidated into fence.h.
Also introduce RISCV_FENCE_ASM to make fence macro more reusable.

Signed-off-by: Eric Chan <ericchancf@google.com>
Reviewed-by: Andrea Parri <parri.andrea@gmail.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Tested-by: Samuel Holland <samuel.holland@sifive.com>
Link: https://lore.kernel.org/r/20240217131316.3668927-1-ericchancf@google.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

diff --git a/arch/riscv/include/asm/atomic.h b/arch/riscv/include/asm/atomic.h
index 31e6e2e7cc181456fdd3233bbafc37bb175bf6f8..0e0522e588ca6e5378589e5c443c37e97cc5fa53 100644 (file)
--- a/arch/riscv/include/asm/atomic.h
+++ b/arch/riscv/include/asm/atomic.h
@@ -17,7 +17,6 @@
 #endif
 
 #include <asm/cmpxchg.h>
-#include <asm/barrier.h>
 
 #define __atomic_acquire_fence()                                       \
        __asm__ __volatile__(RISCV_ACQUIRE_BARRIER "" ::: "memory")

diff --git a/arch/riscv/include/asm/barrier.h b/arch/riscv/include/asm/barrier.h
index 173b44a989f8bad72e59e267dcffc9849c66ea92..15857dbc2279f4d233911e6b7b6641efeca0a813 100644 (file)
--- a/arch/riscv/include/asm/barrier.h
+++ b/arch/riscv/include/asm/barrier.h
@@ -11,13 +11,12 @@
 #define _ASM_RISCV_BARRIER_H
 
 #ifndef __ASSEMBLY__
+#include <asm/fence.h>
 
 #define nop()          __asm__ __volatile__ ("nop")
 #define __nops(n)      ".rept  " #n "\nnop\n.endr\n"
 #define nops(n)                __asm__ __volatile__ (__nops(n))
 
-#define RISCV_FENCE(p, s) \
-       __asm__ __volatile__ ("fence " #p "," #s : : : "memory")
 
 /* These barriers need to enforce ordering on both devices or memory. */
 #define __mb()         RISCV_FENCE(iorw, iorw)

diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h
index a608e4d1a0a4110f3ae623ce9f3e9c27ace7b25e..2fee65cc8443246c07ca1f2c53e896cad426ae77 100644 (file)
--- a/arch/riscv/include/asm/cmpxchg.h
+++ b/arch/riscv/include/asm/cmpxchg.h
@@ -8,7 +8,6 @@
 
 #include <linux/bug.h>
 
-#include <asm/barrier.h>
 #include <asm/fence.h>
 
 #define __xchg_relaxed(ptr, new, size)                                 \

diff --git a/arch/riscv/include/asm/fence.h b/arch/riscv/include/asm/fence.h
index 6c26c44dfcd625bfcf80a4afe359cb15c1a84911..6bcd80325dfc1724aee2e5863ba39881ebea120b 100644 (file)
--- a/arch/riscv/include/asm/fence.h
+++ b/arch/riscv/include/asm/fence.h
@@ -1,10 +1,14 @@
 #ifndef _ASM_RISCV_FENCE_H
 #define _ASM_RISCV_FENCE_H
 
+#define RISCV_FENCE_ASM(p, s)          "\tfence " #p "," #s "\n"
+#define RISCV_FENCE(p, s) \
+       ({ __asm__ __volatile__ (RISCV_FENCE_ASM(p, s) : : : "memory"); })
+
 #ifdef CONFIG_SMP
-#define RISCV_ACQUIRE_BARRIER          "\tfence r , rw\n"
-#define RISCV_RELEASE_BARRIER          "\tfence rw,  w\n"
-#define RISCV_FULL_BARRIER             "\tfence rw, rw\n"
+#define RISCV_ACQUIRE_BARRIER          RISCV_FENCE_ASM(r, rw)
+#define RISCV_RELEASE_BARRIER          RISCV_FENCE_ASM(rw, w)
+#define RISCV_FULL_BARRIER             RISCV_FENCE_ASM(rw, rw)
 #else
 #define RISCV_ACQUIRE_BARRIER
 #define RISCV_RELEASE_BARRIER

diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h
index 42497d487a174642bee085b3a950ee6211396fd3..1c5c641075d2fd48d2f20fa8993875261ada4eb4 100644 (file)
--- a/arch/riscv/include/asm/io.h
+++ b/arch/riscv/include/asm/io.h
@@ -47,10 +47,10 @@
  * sufficient to ensure this works sanely on controllers that support I/O
  * writes.
  */
-#define __io_pbr()     __asm__ __volatile__ ("fence io,i"  : : : "memory");
-#define __io_par(v)    __asm__ __volatile__ ("fence i,ior" : : : "memory");
-#define __io_pbw()     __asm__ __volatile__ ("fence iow,o" : : : "memory");
-#define __io_paw()     __asm__ __volatile__ ("fence o,io"  : : : "memory");
+#define __io_pbr()     RISCV_FENCE(io, i)
+#define __io_par(v)    RISCV_FENCE(i, ior)
+#define __io_pbw()     RISCV_FENCE(iow, o)
+#define __io_paw()     RISCV_FENCE(o, io)
 
 /*
  * Accesses from a single hart to a single I/O address must be ordered.  This

diff --git a/arch/riscv/include/asm/mmio.h b/arch/riscv/include/asm/mmio.h
index 4c58ee7f95ecfa65ae11de96eda76347e747fe56..06cadfd7a237aceec28e4a3db693b1ae57db8e8e 100644 (file)
--- a/arch/riscv/include/asm/mmio.h
+++ b/arch/riscv/include/asm/mmio.h
@@ -12,6 +12,7 @@
 #define _ASM_RISCV_MMIO_H
 
 #include <linux/types.h>
+#include <asm/fence.h>
 #include <asm/mmiowb.h>
 
 /* Generic IO read/write.  These perform native-endian accesses. */
@@ -131,8 +132,8 @@ static inline u64 __raw_readq(const volatile void __iomem *addr)
  * doesn't define any ordering between the memory space and the I/O space.
  */
 #define __io_br()      do {} while (0)
-#define __io_ar(v)     ({ __asm__ __volatile__ ("fence i,ir" : : : "memory"); })
-#define __io_bw()      ({ __asm__ __volatile__ ("fence w,o" : : : "memory"); })
+#define __io_ar(v)     RISCV_FENCE(i, ir)
+#define __io_bw()      RISCV_FENCE(w, o)
 #define __io_aw()      mmiowb_set_pending()
 
 #define readb(c)       ({ u8  __v; __io_br(); __v = readb_cpu(c); __io_ar(__v); __v; })

diff --git a/arch/riscv/include/asm/mmiowb.h b/arch/riscv/include/asm/mmiowb.h
index 0b2333e71fdc5d52b06f2b96d88ab7f39ff37d70..52ce4a399d9b2b1ecab80ba7b7525c2e148cee35 100644 (file)
--- a/arch/riscv/include/asm/mmiowb.h
+++ b/arch/riscv/include/asm/mmiowb.h
@@ -7,7 +7,7 @@
  * "o,w" is sufficient to ensure that all writes to the device have completed
  * before the write to the spinlock is allowed to commit.
  */
-#define mmiowb()       __asm__ __volatile__ ("fence o,w" : : : "memory");
+#define mmiowb()       RISCV_FENCE(o, w)
 
 #include <linux/smp.h>
 #include <asm-generic/mmiowb.h>