drm/amd/sriov skip vcn powergating and dec_ring_test

1.Skip decode_ring test in VF, because VCN in SRIOV does not
support direct register read/write.

2.Skip powergating configuration in hw fini because
VCN3.0 SRIOV doesn't support powergating.

V2: delete unneccessary white lines and refine implementation.

Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 15ff30c53e248a14a663d0a0b72a38934dc7b8de..92a55e40bc484ddb3159f4b8ac841c82a8a1baf0 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -421,6 +421,10 @@ int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring)
        unsigned i;
        int r;
 
+       /* VCN in SRIOV does not support direct register read/write */
+       if (amdgpu_sriov_vf(adev))
+               return 0;
+
        WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);
        r = amdgpu_ring_alloc(ring, 3);
        if (r)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index 0a0ca10bf55bd9d65c48153db28bf74d7864dd3a..910a4a32ff78f8f67f38d487b7b680319c14020b 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -354,11 +354,13 @@ static int vcn_v3_0_hw_fini(void *handle)
 
                ring = &adev->vcn.inst[i].ring_dec;
 
-               if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
-                       (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
-                       RREG32_SOC15(VCN, i, mmUVD_STATUS)))
-                       vcn_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
-
+               if (!amdgpu_sriov_vf(adev)) {
+                       if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
+                                       (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
+                                        RREG32_SOC15(VCN, i, mmUVD_STATUS))) {
+                               vcn_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
+                       }
+               }
                ring->sched.ready = false;
 
                for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
@@ -1861,6 +1863,15 @@ static int vcn_v3_0_set_powergating_state(void *handle,
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
        int ret;
 
+       /* for SRIOV, guest should not control VCN Power-gating
+        * MMSCH FW should control Power-gating and clock-gating
+        * guest should avoid touching CGC and PG
+        */
+       if (amdgpu_sriov_vf(adev)) {
+               adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
+               return 0;
+       }
+
        if(state == adev->vcn.cur_state)
                return 0;