drm/amd/display: Implement bias and scale pre scl

why:
New scaler needs the input to be full range color space. This will also fix
issues that come up due to not having a predefined limited color space matrix
for certain color spaces

how:
Use bias and scale HW to expand the range of limited color spaces to full
before the scaler

Reviewed-by: Krunoslav Kovac <krunoslav.kovac@amd.com>
Signed-off-by: Jerry Zuo <jerry.zuo@amd.com>
Signed-off-by: Relja Vojvodic <relja.vojvodic@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
index 87e36d51c56d802f8f9ebf73873442b1900b6083..9e42a0128baa397f3bdf09c18c58f3b9c2f7d0da 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
@@ -901,12 +901,12 @@ void hwss_program_bias_and_scale(union block_sequence_params *params)
        struct pipe_ctx *pipe_ctx = params->program_bias_and_scale_params.pipe_ctx;
        struct dpp *dpp = pipe_ctx->plane_res.dpp;
        struct dc_plane_state *plane_state = pipe_ctx->plane_state;
-       struct dc_bias_and_scale bns_params = {0};
+       struct dc_bias_and_scale bns_params = plane_state->bias_and_scale;
 
        //TODO :for CNVC set scale and bias registers if necessary
-       build_prescale_params(&bns_params, plane_state);
-       if (dpp->funcs->dpp_program_bias_and_scale)
+       if (dpp->funcs->dpp_program_bias_and_scale) {
                dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
+       }
 }
 
 void hwss_power_on_mpc_mem_pwr(union block_sequence_params *params)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 4c9bb913125d88499b14e58bee7efbeaf14ad54f..83fe13f5a367d612af64ee71aa6dc0e2b4e9751c 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1292,7 +1292,7 @@ struct dc_plane_state {
 
        struct dc_gamma gamma_correction;
        struct dc_transfer_func in_transfer_func;
-       struct dc_bias_and_scale *bias_and_scale;
+       struct dc_bias_and_scale bias_and_scale;
        struct dc_csc_transform input_csc_color_matrix;
        struct fixed31_32 coeff_reduction_factor;
        struct fixed31_32 hdr_mult;

diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c
index e16274fee31d50658fd936b37c93584edc9f3c5f..8473c694bfdc2ecd3d2ea06f3f2ea6f6c0504c67 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c
@@ -59,6 +59,31 @@ void dpp35_dppclk_control(
                                DISPCLK_R_GATE_DISABLE, 0);
 }
 
+void dpp35_program_bias_and_scale_fcnv(
+       struct dpp *dpp_base,
+       struct dc_bias_and_scale *params)
+{
+       struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
+
+       if (!params->bias_and_scale_valid) {
+               REG_SET(FCNV_FP_BIAS_R, 0, FCNV_FP_BIAS_R, 0);
+               REG_SET(FCNV_FP_BIAS_G, 0, FCNV_FP_BIAS_G, 0);
+               REG_SET(FCNV_FP_BIAS_B, 0, FCNV_FP_BIAS_B, 0);
+
+               REG_SET(FCNV_FP_SCALE_R, 0, FCNV_FP_SCALE_R, 0x1F000);
+               REG_SET(FCNV_FP_SCALE_G, 0, FCNV_FP_SCALE_G, 0x1F000);
+               REG_SET(FCNV_FP_SCALE_B, 0, FCNV_FP_SCALE_B, 0x1F000);
+       } else {
+               REG_SET(FCNV_FP_BIAS_R, 0, FCNV_FP_BIAS_R, params->bias_red);
+               REG_SET(FCNV_FP_BIAS_G, 0, FCNV_FP_BIAS_G, params->bias_green);
+               REG_SET(FCNV_FP_BIAS_B, 0, FCNV_FP_BIAS_B, params->bias_blue);
+
+               REG_SET(FCNV_FP_SCALE_R, 0, FCNV_FP_SCALE_R, params->scale_red);
+               REG_SET(FCNV_FP_SCALE_G, 0, FCNV_FP_SCALE_G, params->scale_green);
+               REG_SET(FCNV_FP_SCALE_B, 0, FCNV_FP_SCALE_B, params->scale_blue);
+       }
+}
+
 static struct dpp_funcs dcn35_dpp_funcs = {
        .dpp_program_gamcor_lut         = dpp3_program_gamcor_lut,
        .dpp_read_state                         = dpp30_read_state,
@@ -81,7 +106,7 @@ static struct dpp_funcs dcn35_dpp_funcs = {
        .dpp_program_shaper_lut         = NULL, // CM SHAPER block is removed in DCN3.2 DPP, (it is in MPCC, programmable before or after BLND)
        .dpp_program_3dlut                      = NULL, // CM 3DLUT block is removed in DCN3.2 DPP, (it is in MPCC, programmable before or after BLND)
 
-       .dpp_program_bias_and_scale     = NULL,
+       .dpp_program_bias_and_scale     = dpp35_program_bias_and_scale_fcnv,
        .dpp_cnv_set_alpha_keyer        = dpp2_cnv_set_alpha_keyer,
        .set_cursor_attributes          = dpp3_set_cursor_attributes,
        .set_cursor_position            = dpp1_set_cursor_position,

diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.h b/drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.h
index 135872d88219d87fea8b9211289064514c0a66fd..3ca339a16e5b03b878ab0b6d5834ee266f077e92 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.h
@@ -61,4 +61,7 @@ bool dpp35_construct(struct dcn3_dpp *dpp3, struct dc_context *ctx,
 
 void dpp35_set_fgcg(struct dcn3_dpp *dpp, bool enable);
 
+void dpp35_program_bias_and_scale_fcnv(struct dpp *dpp_base,
+               struct dc_bias_and_scale *bias_and_scale);
+
 #endif // __DCN35_DPP_H

diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c
index 7cae18fd7be9c48b2d1aa7ec6099eb529acba4ab..97bf26fa3573898027ada5f6cac701b9b103724c 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c
@@ -30,6 +30,7 @@
 #include "basics/conversion.h"
 #include "dcn30/dcn30_cm_common.h"
 #include "dcn32/dcn32_dpp.h"
+#include "dcn35/dcn35_dpp.h"
 
 #define REG(reg)\
        dpp->tf_regs->reg
@@ -240,7 +241,7 @@ static struct dpp_funcs dcn401_dpp_funcs = {
        .dpp_program_shaper_lut         = NULL, // CM SHAPER block is removed in DCN3.2 DPP, (it is in MPCC, programmable before or after BLND)
        .dpp_program_3dlut                      = NULL, // CM 3DLUT block is removed in DCN3.2 DPP, (it is in MPCC, programmable before or after BLND)
 
-       .dpp_program_bias_and_scale     = NULL,
+       .dpp_program_bias_and_scale     = dpp35_program_bias_and_scale_fcnv,
        .dpp_cnv_set_alpha_keyer        = dpp2_cnv_set_alpha_keyer,
        .set_cursor_attributes          = dpp401_set_cursor_attributes,
        .set_cursor_position            = dpp401_set_cursor_position,

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
index ea9bedf65d848295c424696ce8e3c48650850f85..9a00479f04178eb54c4454f24494b873354d3e0f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
@@ -1698,7 +1698,7 @@ static void dcn20_update_dchubp_dpp(
                        plane_state->update_flags.bits.input_csc_change ||
                        plane_state->update_flags.bits.color_space_change ||
                        plane_state->update_flags.bits.coeff_reduction_change) {
-               struct dc_bias_and_scale bns_params = {0};
+               struct dc_bias_and_scale bns_params = plane_state->bias_and_scale;
 
                // program the input csc
                dpp->funcs->dpp_setup(dpp,
@@ -1715,7 +1715,6 @@ static void dcn20_update_dchubp_dpp(
                }
                if (dpp->funcs->dpp_program_bias_and_scale) {
                        //TODO :for CNVC set scale and bias registers if necessary
-                       build_prescale_params(&bns_params, plane_state);
                        dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
                }
        }

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
index 27bba47186e92179d44ab13af437341ba191d2ca..41c76ba9ba569d3aaec05c116b021687d5411d21 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
@@ -217,12 +217,13 @@ enum optc_dsc_mode {
 };
 
 struct dc_bias_and_scale {
-       uint16_t scale_red;
-       uint16_t bias_red;
-       uint16_t scale_green;
-       uint16_t bias_green;
-       uint16_t scale_blue;
-       uint16_t bias_blue;
+       uint32_t scale_red;
+       uint32_t bias_red;
+       uint32_t scale_green;
+       uint32_t bias_green;
+       uint32_t scale_blue;
+       uint32_t bias_blue;
+       bool bias_and_scale_valid;
 };
 
 enum test_pattern_dyn_range {