clk: clocking-wizard: Move clocking-wizard out

Add clocking wizard driver to clk.
And delete the driver from the staging as it is in drivers/clk.

Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Link: https://lore.kernel.org/r/20220411100443.15132-3-shubhrajyoti.datta@xilinx.com
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/xilinx/Kconfig b/drivers/clk/xilinx/Kconfig
index 5224114176ed60db3b4168467894c1453b481473..5b99ecfd2f069ce37088d167191f23e40bc91fef 100644 (file)
--- a/drivers/clk/xilinx/Kconfig
+++ b/drivers/clk/xilinx/Kconfig
@@ -17,3 +17,14 @@ config XILINX_VCU
          To compile this driver as a module, choose M here: the
          module will be called xlnx_vcu.
 
+config COMMON_CLK_XLNX_CLKWZRD
+       tristate "Xilinx Clocking Wizard"
+       depends on COMMON_CLK && OF
+       help
+         Support for the Xilinx Clocking Wizard IP core clock generator.
+         Adds support for clocking wizard and compatible.
+         This driver supports the Xilinx clocking wizard programmable clock
+         synthesizer. The number of output is configurable in the design.
+
+         If unsure, say N.
+

diff --git a/drivers/clk/xilinx/Makefile b/drivers/clk/xilinx/Makefile
index dee8fd51e303281968e2c2f198d403a5ac573473..7ac1789c6b1bcaef4f632180669a63c69e1b57d1 100644 (file)
--- a/drivers/clk/xilinx/Makefile
+++ b/drivers/clk/xilinx/Makefile
@@ -1,2 +1,3 @@
 # SPDX-License-Identifier: GPL-2.0
 obj-$(CONFIG_XILINX_VCU)       += xlnx_vcu.o
+obj-$(CONFIG_COMMON_CLK_XLNX_CLKWZRD)  += clk-xlnx-clock-wizard.o

diff --git a/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c b/drivers/clk/xilinx/clk-xlnx-clock-wizard.c
similarity index 99%
rename from drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c
rename to drivers/clk/xilinx/clk-xlnx-clock-wizard.c
index 39367712ef540ab62ff6c21329a2cd7f111e32b3..ec377f0d569b81a8531fecdf9993dc70a1d68e02 100644 (file)
--- a/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c
+++ b/drivers/clk/xilinx/clk-xlnx-clock-wizard.c
@@ -2,9 +2,10 @@
 /*
  * Xilinx 'Clocking Wizard' driver
  *
- *  Copyright (C) 2013 - 2014 Xilinx
+ *  Copyright (C) 2013 - 2021 Xilinx
  *
  *  Sören Brinkmann <soren.brinkmann@xilinx.com>
+ *
  */
 
 #include <linux/platform_device.h>

diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig
index 3bd80f9695ac069df5f63fd899461af4c2d51eed..211436b40c0a109424b3ec946569d44ae0f1cca9 100644 (file)
--- a/drivers/staging/Kconfig
+++ b/drivers/staging/Kconfig
@@ -62,8 +62,6 @@ source "drivers/staging/gdm724x/Kconfig"
 
 source "drivers/staging/fwserial/Kconfig"
 
-source "drivers/staging/clocking-wizard/Kconfig"
-
 source "drivers/staging/fbtft/Kconfig"
 
 source "drivers/staging/most/Kconfig"

diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile
index 1d9ae39fea14a14258edf6fc313e15a7a1b54eae..f1be26a5f222ce521d4847377835bef1873642fb 100644 (file)
--- a/drivers/staging/Makefile
+++ b/drivers/staging/Makefile
@@ -21,7 +21,6 @@ obj-$(CONFIG_MFD_NVEC)                += nvec/
 obj-$(CONFIG_STAGING_BOARD)    += board/
 obj-$(CONFIG_LTE_GDM724X)      += gdm724x/
 obj-$(CONFIG_FIREWIRE_SERIAL)  += fwserial/
-obj-$(CONFIG_COMMON_CLK_XLNX_CLKWZRD)  += clocking-wizard/
 obj-$(CONFIG_FB_TFT)           += fbtft/
 obj-$(CONFIG_MOST)             += most/
 obj-$(CONFIG_KS7010)           += ks7010/

diff --git a/drivers/staging/clocking-wizard/Kconfig b/drivers/staging/clocking-wizard/Kconfig
deleted file mode 100644 (file)
index 2324b5d..0000000
--- a/drivers/staging/clocking-wizard/Kconfig
+++ /dev/null
@@ -1,10 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Xilinx Clocking Wizard Driver
-#
-
-config COMMON_CLK_XLNX_CLKWZRD
-       tristate "Xilinx Clocking Wizard"
-       depends on COMMON_CLK && OF && HAS_IOMEM
-       help
-         Support for the Xilinx Clocking Wizard IP core clock generator.

diff --git a/drivers/staging/clocking-wizard/Makefile b/drivers/staging/clocking-wizard/Makefile
deleted file mode 100644 (file)
index b1f9152..0000000
--- a/drivers/staging/clocking-wizard/Makefile
+++ /dev/null
@@ -1,2 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-obj-$(CONFIG_COMMON_CLK_XLNX_CLKWZRD)  += clk-xlnx-clock-wizard.o

diff --git a/drivers/staging/clocking-wizard/TODO b/drivers/staging/clocking-wizard/TODO
deleted file mode 100644 (file)
index c7e1dc5..0000000
--- a/drivers/staging/clocking-wizard/TODO
+++ /dev/null
@@ -1,13 +0,0 @@
-TODO:
-       - support for fractional multiplier
-       - support for fractional divider (output 0 only)
-       - support for set_rate() operations (may benefit from Stephen Boyd's
-         refactoring of the clk primitives:
-         https://lore.kernel.org/lkml/1409957256-23729-1-git-send-email-sboyd@codeaurora.org)
-       - review arithmetic
-         - overflow after multiplication?
-         - maximize accuracy before divisions
-
-Patches to:
-       Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-       Sören Brinkmann <soren.brinkmann@xilinx.com>

diff --git a/drivers/staging/clocking-wizard/dt-binding.txt b/drivers/staging/clocking-wizard/dt-binding.txt
deleted file mode 100644 (file)
index efb67ff..0000000
--- a/drivers/staging/clocking-wizard/dt-binding.txt
+++ /dev/null
@@ -1,30 +0,0 @@
-Binding for Xilinx Clocking Wizard IP Core
-
-This binding uses the common clock binding[1]. Details about the devices can be
-found in the product guide[2].
-
-[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-[2] Clocking Wizard Product Guide
-https://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v5_1/pg065-clk-wiz.pdf
-
-Required properties:
- - compatible: Must be 'xlnx,clocking-wizard'
- - reg: Base and size of the cores register space
- - clocks: Handle to input clock
- - clock-names: Tuple containing 'clk_in1' and 's_axi_aclk'
- - clock-output-names: Names for the output clocks
-
-Optional properties:
- - speed-grade: Speed grade of the device (valid values are 1..3)
-
-Example:
-       clock-generator@40040000 {
-               reg = <0x40040000 0x1000>;
-               compatible = "xlnx,clocking-wizard";
-               speed-grade = <1>;
-               clock-names = "clk_in1", "s_axi_aclk";
-               clocks = <&clkc 15>, <&clkc 15>;
-               clock-output-names = "clk_out0", "clk_out1", "clk_out2",
-                                    "clk_out3", "clk_out4", "clk_out5",
-                                    "clk_out6", "clk_out7";
-       };