drm/i915: Use ring->flush() instead of MI_FLUSH

Use the ring abstraction to hide the details of having choose the
appropriate flushing method.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4b6812015056f7f69ee8ff732afacd73aca793d8..790ffec135df5f67a9438a1778a1bb92bcc772f8 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1001,6 +1001,10 @@ void i915_gem_retire_requests(struct drm_device *dev);
 void i915_gem_reset_flushing_list(struct drm_device *dev);
 void i915_gem_reset_inactive_gpu_domains(struct drm_device *dev);
 void i915_gem_clflush_object(struct drm_gem_object *obj);
+void i915_gem_flush_ring(struct drm_device *dev,
+                        struct intel_ring_buffer *ring,
+                        uint32_t invalidate_domains,
+                        uint32_t flush_domains);
 int i915_gem_object_set_domain(struct drm_gem_object *obj,
                               uint32_t read_domains,
                               uint32_t write_domain);

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 7b33b4d5ebff3b6ba2521413196f4763e957e09f..b242530ffcbd76ef7598fa9e152668360e364a13 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1908,7 +1908,7 @@ i915_wait_request(struct drm_device *dev, uint32_t seqno,
        return i915_do_wait_request(dev, seqno, 1, ring);
 }
 
-static void
+void
 i915_gem_flush_ring(struct drm_device *dev,
                    struct intel_ring_buffer *ring,
                    uint32_t invalidate_domains,

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c3f0400963deee3a741b765d78643cb43c0d2ab4..0505ddb76a10992524e73c7285a7350a5feb718f 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5056,24 +5056,23 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
        atomic_inc(&obj_priv->pending_flip);
        work->pending_flip_obj = obj;
 
-       if (was_dirty || IS_GEN3(dev) || IS_GEN2(dev)) {
-               BEGIN_LP_RING(2);
-               if (IS_GEN3(dev) || IS_GEN2(dev)) {
-                       u32 flip_mask;
+       /* Schedule the pipelined flush */
+       if (was_dirty)
+               i915_gem_flush_ring(dev, obj_priv->ring, 0, was_dirty);
 
-                       /* Can't queue multiple flips, so wait for the previous
-                        * one to finish before executing the next.
-                        */
+       if (IS_GEN3(dev) || IS_GEN2(dev)) {
+               u32 flip_mask;
 
-                       if (intel_crtc->plane)
-                               flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
-                       else
-                               flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
-
-                       OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
-               } else
-                       OUT_RING(MI_NOOP);
-               OUT_RING(MI_FLUSH);
+               /* Can't queue multiple flips, so wait for the previous
+                * one to finish before executing the next.
+                */
+               BEGIN_LP_RING(2);
+               if (intel_crtc->plane)
+                       flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
+               else
+                       flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
+               OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
+               OUT_RING(MI_NOOP);
                ADVANCE_LP_RING();
        }