drm/amd/display: Update dml ssb from pmfw clock table

[why]
Need to use real clock table

[How]
Update the clock table

Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Muhammad Ahmed <ahmed.ahmed@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c
index f1d776f3954365d4ef4e96dd2c5c729a046dc90f..afc14259a7b59311df3e2dacbc0cb6157c0ee39d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c
@@ -698,7 +698,7 @@ static const struct dc_debug_options debug_defaults_drv = {
        .underflow_assert_delay_us = 0xFFFFFFFF,
        .dwb_fi_phase = -1, // -1 = disable,
        .dmub_command_table = true,
-       .pstate_enabled = false,
+       .pstate_enabled = true,
        .use_max_lb = true,
        .enable_mem_low_power = {
                .bits = {
@@ -1840,7 +1840,7 @@ static bool dcn35_resource_construct(
 
        /* Use pipe context based otg sync logic */
        dc->config.use_pipe_ctx_sync_logic = true;
-       dc->config.use_default_clock_table = true;
+       dc->config.use_default_clock_table = false;
        /* read VBIOS LTTPR caps */
        {
                if (ctx->dc_bios->funcs->get_lttpr_caps) {

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
index 4d5ee2aad9e402bc8d4450df567d0305cb462367..be345f470b253f13226ad4a4f2f072900eac6992 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
@@ -205,29 +205,7 @@ void dcn35_build_wm_range_table_fpu(struct clk_mgr *clk_mgr)
        //TODO
 }
 
-void dcn35_patch_dpm_table(struct clk_bw_params *bw_params)
-{
-       int i;
-       unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0,
-                       max_phyclk_mhz = 0, max_dtbclk_mhz = 0, max_fclk_mhz = 0, max_uclk_mhz = 0;
-
-       for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
-               if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)
-                       max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
-               if (bw_params->clk_table.entries[i].fclk_mhz > max_fclk_mhz)
-                       max_fclk_mhz = bw_params->clk_table.entries[i].fclk_mhz;
-               if (bw_params->clk_table.entries[i].memclk_mhz > max_uclk_mhz)
-                       max_uclk_mhz = bw_params->clk_table.entries[i].memclk_mhz;
-               if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz)
-                       max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
-               if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz)
-                       max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
-               if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz)
-                       max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
-               if (bw_params->clk_table.entries[i].dtbclk_mhz > max_dtbclk_mhz)
-                       max_dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz;
-       }
-}
+
 /*
  * dcn35_update_bw_bounding_box
  *

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.h b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.h
index b122ffdcc30af7582cbc60ed7b174a3439b0338c..e8d5a170893e3b650b67d77f61db08be13e05108 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.h
@@ -34,8 +34,6 @@ void dcn35_build_wm_range_table_fpu(struct clk_mgr *clk_mgr);
 void dcn35_update_bw_bounding_box_fpu(struct dc *dc,
                                      struct clk_bw_params *bw_params);
 
-void dcn35_patch_dpm_table(struct clk_bw_params *bw_params);
-
 int dcn35_populate_dml_pipes_from_context_fpu(struct dc *dc,
                                              struct dc_state *context,
                                              display_e2e_pipe_params_st *pipes,