#include <linux/ssb/ssb.h>
 
+#include <linux/mtd/physmap.h>
 #include <linux/serial.h>
 #include <linux/serial_core.h>
 #include <linux/serial_reg.h>
 
 #include "ssb_private.h"
 
+static const char *part_probes[] = { "bcm47xxpart", NULL };
+
+static struct physmap_flash_data ssb_pflash_data = {
+       .part_probe_types       = part_probes,
+};
+
+static struct resource ssb_pflash_resource = {
+       .name   = "ssb_pflash",
+       .flags  = IORESOURCE_MEM,
+};
+
+struct platform_device ssb_pflash_dev = {
+       .name           = "physmap-flash",
+       .dev            = {
+               .platform_data  = &ssb_pflash_data,
+       },
+       .resource       = &ssb_pflash_resource,
+       .num_resources  = 1,
+};
 
 static inline u32 mips_read32(struct ssb_mipscore *mcore,
                              u16 offset)
                pflash->buswidth = 2;
                pflash->window = SSB_FLASH1;
                pflash->window_size = SSB_FLASH1_SZ;
-               return;
+               goto ssb_pflash;
        }
 
        /* There is ChipCommon, so use it to read info about flash */
                        pflash->buswidth = 2;
                break;
        }
+
+ssb_pflash:
+       if (pflash->present) {
+               ssb_pflash_data.width = pflash->buswidth;
+               ssb_pflash_resource.start = pflash->window;
+               ssb_pflash_resource.end = pflash->window + pflash->window_size;
+       }
 }
 
 u32 ssb_cpu_clock(struct ssb_mipscore *mcore)
 
                dev_idx++;
        }
 
+#ifdef CONFIG_SSB_DRIVER_MIPS
+       if (bus->mipscore.pflash.present) {
+               err = platform_device_register(&ssb_pflash_dev);
+               if (err)
+                       pr_err("Error registering parallel flash\n");
+       }
+#endif
+
        return 0;
 error:
        /* Unwind the already registered devices. */
 
 }
 #endif /* CONFIG_SSB_SFLASH */
 
+#ifdef CONFIG_SSB_DRIVER_MIPS
+extern struct platform_device ssb_pflash_dev;
+#endif
+
 #ifdef CONFIG_SSB_DRIVER_EXTIF
 extern u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks);
 extern u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);