drm/amd/display: Change initializer to single brace

Acked-by: Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index d54592b573e9dbde79043c327aeae3ac339f013e..6db611f9f554c7d9e5243eca5626ce868e4b73e4 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -674,13 +674,13 @@ static void query_hdcp_capability(enum signal_type signal, struct dc_link *link)
 
 static void read_current_link_settings_on_detect(struct dc_link *link)
 {
-       union lane_count_set lane_count_set = { {0} };
+       union lane_count_set lane_count_set = {0};
        uint8_t link_bw_set;
        uint8_t link_rate_set;
        uint32_t read_dpcd_retry_cnt = 10;
        enum dc_status status = DC_ERROR_UNEXPECTED;
        int i;
-       union max_down_spread max_down_spread = { {0} };
+       union max_down_spread max_down_spread = {0};
 
        // Read DPCD 00101h to find out the number of lanes currently set
        for (i = 0; i < read_dpcd_retry_cnt; i++) {
@@ -3279,8 +3279,7 @@ static void update_mst_stream_alloc_table(
        struct stream_encoder *stream_enc,
        const struct dp_mst_stream_allocation_table *proposed_table)
 {
-       struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = {
-                       { 0 } };
+       struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = { 0 };
        struct link_mst_stream_allocation *dc_alloc;
 
        int i;

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
index b0f1cd7268c8cf619b4946dfe950a4f1b12eec03..471a67a64299e791ba6434855cf49d9516d872ea 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
@@ -763,7 +763,7 @@ void dal_ddc_service_read_scdc_data(struct ddc_service *ddc_service)
        dal_ddc_service_query_ddc_data(ddc_service, slave_address, &offset,
                        sizeof(offset), &tmds_config, sizeof(tmds_config));
        if (tmds_config & 0x1) {
-               union hdmi_scdc_status_flags_data status_data = { {0} };
+               union hdmi_scdc_status_flags_data status_data = {0};
                uint8_t scramble_status = 0;
 
                offset = HDMI_SCDC_SCRAMBLER_STATUS;

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 8e0b40c7a1eed666476523653a85ab7157cb74db..296b0defcd1c3c3690e234e8b5b72494568c3cac 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -259,7 +259,7 @@ static void dpcd_set_training_pattern(
        struct dc_link *link,
        enum dc_dp_training_pattern training_pattern)
 {
-       union dpcd_training_pattern dpcd_pattern = { {0} };
+       union dpcd_training_pattern dpcd_pattern = {0};
 
        dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
                        dc_dp_training_pattern_to_dpcd_training_pattern(
@@ -401,8 +401,8 @@ enum dc_status dpcd_set_link_settings(
        uint8_t rate;
        enum dc_status status;
 
-       union down_spread_ctrl downspread = { {0} };
-       union lane_count_set lane_count_set = { {0} };
+       union down_spread_ctrl downspread = {0};
+       union lane_count_set lane_count_set = {0};
 
        downspread.raw = (uint8_t)
        (lt_settings->link_settings.link_spread);
@@ -520,7 +520,7 @@ static void dpcd_set_lt_pattern_and_lane_settings(
        uint32_t dpcd_base_lt_offset;
 
        uint8_t dpcd_lt_buffer[5] = {0};
-       union dpcd_training_pattern dpcd_pattern = { {0} };
+       union dpcd_training_pattern dpcd_pattern = { 0 };
        uint32_t size_in_bytes;
        bool edp_workaround = false; /* TODO link_prop.INTERNAL */
        dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET;
@@ -1266,8 +1266,8 @@ static enum link_training_result perform_channel_equalization_sequence(
        uint32_t retries_ch_eq;
        uint32_t wait_time_microsec;
        enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
-       union lane_align_status_updated dpcd_lane_status_updated = { {0} };
-       union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
+       union lane_align_status_updated dpcd_lane_status_updated = {0};
+       union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};
 
        /* Note: also check that TPS4 is a supported feature*/
 
@@ -1487,7 +1487,7 @@ static inline enum link_training_result dp_transition_to_video_idle(
        struct link_training_settings *lt_settings,
        enum link_training_result status)
 {
-       union lane_count_set lane_count_set = { {0} };
+       union lane_count_set lane_count_set = {0};
 
        /* 4. mainlink output idle pattern*/
        dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
@@ -1800,7 +1800,7 @@ static enum dc_status configure_lttpr_mode_non_transparent(
 
 static void repeater_training_done(struct dc_link *link, uint32_t offset)
 {
-       union dpcd_training_pattern dpcd_pattern = { {0} };
+       union dpcd_training_pattern dpcd_pattern = {0};
 
        const uint32_t dpcd_base_lt_offset =
                        DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
@@ -2078,8 +2078,8 @@ static enum link_training_result dp_perform_128b_132b_channel_eq_done_sequence(
        uint32_t aux_rd_interval = 0;
        uint32_t wait_time = 0;
        struct link_training_settings req_settings;
-       union lane_align_status_updated dpcd_lane_status_updated = { {0} };
-       union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
+       union lane_align_status_updated dpcd_lane_status_updated = {0};
+       union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};
        enum link_training_result status = LINK_TRAINING_SUCCESS;
 
        /* Transmit 128b/132b_TPS1 over Main-Link and Set TRAINING_PATTERN_SET to 01h */
@@ -2149,8 +2149,8 @@ static enum link_training_result dp_perform_128b_132b_cds_done_sequence(
        /* Assumption: assume hardware has transmitted eq pattern */
        enum link_training_result status = LINK_TRAINING_SUCCESS;
        struct link_training_settings req_settings;
-       union lane_align_status_updated dpcd_lane_status_updated = { {0} };
-       union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
+       union lane_align_status_updated dpcd_lane_status_updated = {0};
+       union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};
        uint32_t wait_time = 0;
 
        /* initiate CDS done sequence */
@@ -4065,8 +4065,8 @@ void dc_link_dp_handle_link_loss(struct dc_link *link)
 bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd_irq_dpcd_data, bool *out_link_loss,
                                                        bool defer_handling, bool *has_left_work)
 {
-       union hpd_irq_data hpd_irq_dpcd_data = { { { {0} } } };
-       union device_service_irq device_service_clear = { { 0 } };
+       union hpd_irq_data hpd_irq_dpcd_data = {0};
+       union device_service_irq device_service_clear = {0};
        enum dc_status result;
        bool status = false;
 
@@ -5939,7 +5939,7 @@ bool is_edp_ilr_optimization_required(struct dc_link *link, struct dc_crtc_timin
        uint8_t link_bw_set;
        uint8_t link_rate_set;
        uint32_t req_bw;
-       union lane_count_set lane_count_set = { {0} };
+       union lane_count_set lane_count_set = {0};
 
        ASSERT(link || crtc_timing); // invalid input
 

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index bc3ec05bf34b5a351876f54bab9660db0e339786..aa2d430f2a1ab25c32d4505b18f0d39ace447706 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2304,8 +2304,8 @@ static void mmhub_read_vm_context0_settings(struct dcn10_hubp *hubp1,
 void dcn10_program_pte_vm(struct dce_hwseq *hws, struct hubp *hubp)
 {
        struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
-       struct vm_system_aperture_param apt = { {{ 0 } } };
-       struct vm_context0_param vm0 = { { { 0 } } };
+       struct vm_system_aperture_param apt = {0};
+       struct vm_context0_param vm0 = {0};
 
        mmhub_read_vm_system_aperture_settings(hubp1, &apt, hws);
        mmhub_read_vm_context0_settings(hubp1, &vm0, hws);
@@ -2478,7 +2478,7 @@ void dcn10_update_visual_confirm_color(struct dc *dc, struct pipe_ctx *pipe_ctx,
 void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
 {
        struct hubp *hubp = pipe_ctx->plane_res.hubp;
-       struct mpcc_blnd_cfg blnd_cfg = {{0}};
+       struct mpcc_blnd_cfg blnd_cfg = {0};
        bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
        int mpcc_id;
        struct mpcc *new_mpcc;
@@ -3635,7 +3635,7 @@ void dcn10_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx)
 void dcn10_unblank_stream(struct pipe_ctx *pipe_ctx,
                struct dc_link_settings *link_settings)
 {
-       struct encoder_unblank_param params = { { 0 } };
+       struct encoder_unblank_param params = {0};
        struct dc_stream_state *stream = pipe_ctx->stream;
        struct dc_link *link = stream->link;
        struct dce_hwseq *hws = link->dc->hwseq;

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index fc83744149d9f9f7f5237fb110adb2bbaf83a0a5..cfee456c6c9ab7b136dd9e4cf0d83dcb9f2f0da1 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -2123,7 +2123,7 @@ void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
 void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,
                struct dc_link_settings *link_settings)
 {
-       struct encoder_unblank_param params = { { 0 } };
+       struct encoder_unblank_param params = {0};
        struct dc_stream_state *stream = pipe_ctx->stream;
        struct dc_link *link = stream->link;
        struct dce_hwseq *hws = link->dc->hwseq;
@@ -2298,7 +2298,7 @@ void dcn20_update_visual_confirm_color(struct dc *dc, struct pipe_ctx *pipe_ctx,
 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
 {
        struct hubp *hubp = pipe_ctx->plane_res.hubp;
-       struct mpcc_blnd_cfg blnd_cfg = { {0} };
+       struct mpcc_blnd_cfg blnd_cfg = {0};
        bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha;
        int mpcc_id;
        struct mpcc *new_mpcc;