return ~readl(dc_timer_dev.base + COUNT(TIMER_B));
 }
 
-static void __init digicolor_timer_init(struct device_node *node)
+static int __init digicolor_timer_init(struct device_node *node)
 {
        unsigned long rate;
        struct clk *clk;
        dc_timer_dev.base = of_iomap(node, 0);
        if (!dc_timer_dev.base) {
                pr_err("Can't map registers");
-               return;
+               return -ENXIO;
        }
 
        irq = irq_of_parse_and_map(node, dc_timer_dev.timer_id);
        if (irq <= 0) {
                pr_err("Can't parse IRQ");
-               return;
+               return -EINVAL;
        }
 
        clk = of_clk_get(node, 0);
        if (IS_ERR(clk)) {
                pr_err("Can't get timer clock");
-               return;
+               return PTR_ERR(clk);
        }
        clk_prepare_enable(clk);
        rate = clk_get_rate(clk);
        ret = request_irq(irq, digicolor_timer_interrupt,
                          IRQF_TIMER | IRQF_IRQPOLL, "digicolor_timerC",
                          &dc_timer_dev.ce);
-       if (ret)
+       if (ret) {
                pr_warn("request of timer irq %d failed (%d)\n", irq, ret);
+               return ret;
+       }
 
        dc_timer_dev.ce.cpumask = cpu_possible_mask;
        dc_timer_dev.ce.irq = irq;
 
        clockevents_config_and_register(&dc_timer_dev.ce, rate, 0, 0xffffffff);
+
+       return 0;
 }
-CLOCKSOURCE_OF_DECLARE(conexant_digicolor, "cnxt,cx92755-timer",
+CLOCKSOURCE_OF_DECLARE_RET(conexant_digicolor, "cnxt,cx92755-timer",
                       digicolor_timer_init);