PAR_EL1,        /* Physical Address Register */
        MDSCR_EL1,      /* Monitor Debug System Control Register */
        MDCCINT_EL1,    /* Monitor Debug Comms Channel Interrupt Enable Reg */
+       DISR_EL1,       /* Deferred Interrupt Status Register */
 
        /* Performance Monitors Registers */
        PMCR_EL0,       /* Control Register */
 
 #define SYS_VSESR_EL2                  sys_reg(3, 4, 5, 2, 3)
 #define SYS_FPEXC32_EL2                        sys_reg(3, 4, 5, 3, 0)
 
+#define SYS_VDISR_EL2                  sys_reg(3, 4, 12, 1,  1)
 #define __SYS__AP0Rx_EL2(x)            sys_reg(3, 4, 12, 8, x)
 #define SYS_ICH_AP0R0_EL2              __SYS__AP0Rx_EL2(0)
 #define SYS_ICH_AP0R1_EL2              __SYS__AP0Rx_EL2(1)
 
        ctxt->gp_regs.spsr[KVM_SPSR_EL1]= read_sysreg_el1(spsr);
        ctxt->gp_regs.regs.pc           = read_sysreg_el2(elr);
        ctxt->gp_regs.regs.pstate       = read_sysreg_el2(spsr);
+
+       if (cpus_have_const_cap(ARM64_HAS_RAS_EXTN))
+               ctxt->sys_regs[DISR_EL1] = read_sysreg_s(SYS_VDISR_EL2);
 }
 
 static hyp_alternate_select(__sysreg_call_save_host_state,
        write_sysreg_el1(ctxt->gp_regs.spsr[KVM_SPSR_EL1],spsr);
        write_sysreg_el2(ctxt->gp_regs.regs.pc,         elr);
        write_sysreg_el2(ctxt->gp_regs.regs.pstate,     spsr);
+
+       if (cpus_have_const_cap(ARM64_HAS_RAS_EXTN))
+               write_sysreg_s(ctxt->sys_regs[DISR_EL1], SYS_VDISR_EL2);
 }
 
 static hyp_alternate_select(__sysreg_call_restore_host_state,
 
        { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 },
 
        { SYS_DESC(SYS_VBAR_EL1), NULL, reset_val, VBAR_EL1, 0 },
+       { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 },
 
        { SYS_DESC(SYS_ICC_IAR0_EL1), write_to_read_only },
        { SYS_DESC(SYS_ICC_EOIR0_EL1), read_from_write_only },