drm/amd/display: Make sure to reprogram ODM when resync fifo

Need to reconfigure ODM when resyncing FIFO because on OTG disable we
clear all ODM programming

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
index 8e68e05e3b72fbd6f2d72bc758ea6144717f449d..388404cdeeaaea0d02e18d0e78577cb89e7dc3e6 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
@@ -379,8 +379,25 @@ void dcn314_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc
        for (i = 0; i < dc->res_pool->pipe_count; i++) {
                pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 
-               if (otg_disabled[i])
+               if (otg_disabled[i]) {
+                       int opp_inst[MAX_PIPES] = { pipe->stream_res.opp->inst };
+                       int opp_cnt = 1;
+                       int last_odm_slice_width = resource_get_odm_slice_dst_width(pipe, true);
+                       int odm_slice_width = resource_get_odm_slice_dst_width(pipe, false);
+                       struct pipe_ctx *odm_pipe;
+
+                       for (odm_pipe = pipe->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
+                               opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;
+                               opp_cnt++;
+                       }
+                       if (opp_cnt > 1)
+                               pipe->stream_res.tg->funcs->set_odm_combine(
+                                               pipe->stream_res.tg,
+                                               opp_inst, opp_cnt,
+                                               odm_slice_width,
+                                               last_odm_slice_width);
                        pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
+               }
        }
 }
 

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
index 0d27eec724b49f8a38f1d6d23e8e47cd2f94ffc5..51dfda0e4df92588344d17a1c44c25a048f89d6b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
@@ -1237,8 +1237,25 @@ void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_
        for (i = 0; i < dc->res_pool->pipe_count; i++) {
                pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 
-               if (otg_disabled[i])
+               if (otg_disabled[i]) {
+                       int opp_inst[MAX_PIPES] = { pipe->stream_res.opp->inst };
+                       int opp_cnt = 1;
+                       int last_odm_slice_width = resource_get_odm_slice_dst_width(pipe, true);
+                       int odm_slice_width = resource_get_odm_slice_dst_width(pipe, false);
+                       struct pipe_ctx *odm_pipe;
+
+                       for (odm_pipe = pipe->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
+                               opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;
+                               opp_cnt++;
+                       }
+                       if (opp_cnt > 1)
+                               pipe->stream_res.tg->funcs->set_odm_combine(
+                                               pipe->stream_res.tg,
+                                               opp_inst, opp_cnt,
+                                               odm_slice_width,
+                                               last_odm_slice_width);
                        pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
+               }
        }
 }