KVM: x86: Add support of clear Trace_ToPA_PMI status

Let guests clear the Intel PT ToPA PMI status (bit 55 of
MSR_CORE_PERF_GLOBAL_OVF_CTRL).

Signed-off-by: Luwei Kang <luwei.kang@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
index a9d03af340307db6589376cf3bfb29a533910cdd..275990e3415be00151741e83fd4a305020e1d3a4 100644 (file)
--- a/arch/x86/include/asm/kvm_host.h
+++ b/arch/x86/include/asm/kvm_host.h
@@ -469,6 +469,7 @@ struct kvm_pmu {
        u64 global_ovf_ctrl;
        u64 counter_bitmask[2];
        u64 global_ctrl_mask;
+       u64 global_ovf_ctrl_mask;
        u64 reserved_bits;
        u8 version;
        struct kvm_pmc gp_counters[INTEL_PMC_MAX_GENERIC];

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index be40c094bc496d05a3d3b7681d5bd0caa612a9dc..3bf5d84bb64f1e8452d35564877e4fe26460c7b6 100644 (file)
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -784,6 +784,10 @@
 /* PERF_GLOBAL_OVF_CTL bits */
 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT       55
 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI           (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT)
+#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT              62
+#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF                  (1ULL <<  MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT)
+#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT            63
+#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD                        (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT)
 
 /* Geode defined MSRs */
 #define MSR_GEODE_BUSCONT_CONF0                0x00001900

diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c
index 5ab4a364348e3c10987c33203be4ff6fa97e1e73..f8502c376b3702f8897a35442fff539093fef418 100644 (file)
--- a/arch/x86/kvm/vmx/pmu_intel.c
+++ b/arch/x86/kvm/vmx/pmu_intel.c
@@ -227,7 +227,7 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
                }
                break;
        case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
-               if (!(data & (pmu->global_ctrl_mask & ~(3ull<<62)))) {
+               if (!(data & pmu->global_ovf_ctrl_mask)) {
                        if (!msr_info->host_initiated)
                                pmu->global_status &= ~data;
                        pmu->global_ovf_ctrl = data;
@@ -297,6 +297,12 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu)
        pmu->global_ctrl = ((1ull << pmu->nr_arch_gp_counters) - 1) |
                (((1ull << pmu->nr_arch_fixed_counters) - 1) << INTEL_PMC_IDX_FIXED);
        pmu->global_ctrl_mask = ~pmu->global_ctrl;
+       pmu->global_ovf_ctrl_mask = pmu->global_ctrl_mask
+                       & ~(MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF |
+                           MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD);
+       if (kvm_x86_ops->pt_supported())
+               pmu->global_ovf_ctrl_mask &=
+                               ~MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI;
 
        entry = kvm_find_cpuid_entry(vcpu, 7, 0);
        if (entry &&