Modifications for 0.8.3:
======================================================================
+* Monster-patch by Murray Jensen:
+
+ - completion of Hymod port
+
+ This also includes my "iopin_8260" stuff, which defines a generic
+ interface for manipulating (as opposed to initialising - which is
+ what the ioport config table does) the 8260 i/o pins, plus a
+ method of passing configuration information to linux - probably
+ not of much interest to most people.
+
+ - a new command "immap" - I added this before the "reginfo" command
+ came out - oh well, I think mine is better :-), except it is not
+ complete (it has enough for what I wanted - others might like to
+ implement other bits).
+
+ - added crtlc() changes by ??? (Marius?)
+
+ - the hymod board has an external clock chip that provides a much
+ better source clock for the cpm serial ports - i.e. it divides
+ cleanly so that baud rates up to 230400 are possible (in fact
+ this is what I run the cpm scc serial ports at now) - this
+ required a new "m8260_cpm_extcbrg()" function
+
+ - minor fix to upmconfig() for 8260 port
+
+ - added config of bank 6 in mem controller - needed by hymod i.e.
+ added support for CFG_[BO]R6_PRELIM
+
+ - slight mod to the net/tftp stuff so that the actual byte size of
+ the transferred file is placed into an environment variable. I
+ use this so that I can transfer via tftp and copy into flash all
+ in one command.
+
* Added support for SBC8260 board (Jay Monkman, Marius Groeger)
* Added support for ESTEEM192E board (Conn Clark)
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * hacked for Hymod FPGA support by Murray.Jensen@cmst.csiro.au, 29-Jan-01
+ */
+
+/*
+ * Hymod FPGA command support
+ */
+#include <ppcboot.h>
+#include <command.h>
+#include <net.h>
+#include <asm/iopin_8260.h>
+#include <asm/hymod.h>
+#include <hymod/cmd_fpga.h>
+
+#define LOAD_SUCCESS 0
+#define LOAD_FAIL_NOCONF 1
+#define LOAD_FAIL_NOINIT 2
+#define LOAD_FAIL_NODONE 3
+
+#define STORE_SUCCESS 0
+
+/*
+ * Programming the Hymod FPGAs
+ *
+ * The 8260 io port config table is set up so that the INIT pin is
+ * held Low (Open Drain output 0) - this will delay the automatic
+ * Power-On config until INIT is released (by making it an input).
+ *
+ * If the FPGA has been programmed before, then the assertion of PROGRAM
+ * will initiate configuration (i.e. it begins clearing the RAM).
+ *
+ * When the FPGA is ready to receive configuration data (either after
+ * releasing INIT after Power-On, or after asserting PROGRAM), it will
+ * pull INIT high.
+ *
+ * Notes from Paul Dunn:
+ *
+ * 1. program pin should be forced low for >= 300ns
+ * (about 20 bus clock cycles minimum).
+ *
+ * 2. then wait for init to go high, which signals
+ * that the FPGA has cleared its internal memory
+ * and is ready to load
+ *
+ * 3. perform load writes of entire config file
+ *
+ * 4. wait for done to go high, which should be
+ * within a few bus clock cycles. If done has not
+ * gone high after reasonable period, then load
+ * has not worked (wait several ms?)
+ */
+
+int
+fpga_load(bd_t *bd, int mezz, uchar *addr, ulong size)
+{
+ hymod_conf_t *cp = &bd->bi_hymod_conf;
+ fpga_iopins_t *fpgaio;
+ volatile uchar *fpgabase;
+ volatile uint cnt;
+ uchar *eaddr = addr + size;
+ int result;
+
+ if (mezz) {
+ if (!cp->mezz_mmap[0].prog.exists)
+ return (LOAD_FAIL_NOCONF);
+ fpgabase = (uchar *)cp->mezz_mmap[0].prog.base;
+ fpgaio = &cp->mezz_iopins[0];
+ }
+ else {
+ if (!cp->main_mmap[0].prog.exists)
+ return (LOAD_FAIL_NOCONF);
+ fpgabase = (uchar *)cp->main_mmap[0].prog.base;
+ fpgaio = &cp->main_iopins[0];
+ }
+
+ /* set enable HIGH if required */
+ if (fpgaio->enable_pin.flag)
+ iopin_set_high(&fpgaio->enable_pin);
+
+ /* ensure INIT is released (set it to be an input) */
+ iopin_set_in(&fpgaio->init_pin);
+
+ /* toggle PROG Low then High (will already be Low after Power-On) */
+ iopin_set_low(&fpgaio->prog_pin);
+ udelay(1); /* minimum 300ns - 1usec should do it */
+ iopin_set_high(&fpgaio->prog_pin);
+
+ /* wait for INIT High */
+ cnt = 0;
+ while (!iopin_is_high(&fpgaio->init_pin))
+ if (++cnt == 10000000) {
+ result = LOAD_FAIL_NOINIT;
+ goto done;
+ }
+
+ /* write configuration data */
+ while (addr < eaddr)
+ *fpgabase = *addr++;
+
+ /* wait for DONE High */
+ cnt = 0;
+ while (!iopin_is_high(&fpgaio->done_pin))
+ if (++cnt == 100000000) {
+ result = LOAD_FAIL_NODONE;
+ goto done;
+ }
+
+ /* success */
+ result = LOAD_SUCCESS;
+
+done:
+
+ if (fpgaio->enable_pin.flag)
+ iopin_set_low(&fpgaio->enable_pin);
+
+ return (result);
+}
+
+/* ------------------------------------------------------------------------- */
+
+void
+do_fpga(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+{
+ uchar *addr, *save_addr;
+ ulong size;
+ int mezz, arg, result;
+
+ switch (argc) {
+
+ case 0:
+ case 1:
+ break;
+
+ case 2:
+ if (strcmp(argv[1], "info") == 0) {
+ printf("\nHymod FPGA Info...\n");
+ printf(" Address Size\n");
+ printf(" Main Configuration: 0x%08x %d\n",
+ FPGA_MAIN_CFG_BASE, FPGA_MAIN_CFG_SIZE);
+ printf(" Main Register: 0x%08x %d\n",
+ FPGA_MAIN_REG_BASE, FPGA_MAIN_REG_SIZE);
+ printf(" Main Port: 0x%08x %d\n",
+ FPGA_MAIN_PORT_BASE, FPGA_MAIN_PORT_SIZE);
+ printf(" Mezz Configuration: 0x%08x %d\n",
+ FPGA_MEZZ_CFG_BASE, FPGA_MEZZ_CFG_SIZE);
+ return;
+ }
+ break;
+
+ case 3:
+ if (strcmp(argv[1], "store") == 0) {
+ addr = (uchar *)simple_strtoul(argv[2], NULL, 16);
+
+ save_addr = addr;
+#if 0
+ /* reading config data unimplemented */
+ while VM:more config data
+ *addr++ = *fpga;
+ result = VM:???
+#else
+ result = 0;
+#endif
+
+ if (result == STORE_SUCCESS)
+ printf("SUCCEEDED (%d bytes)\n", addr - save_addr);
+ else
+ printf("FAILED (%d bytes)\n", addr - save_addr);
+ return;
+ }
+ break;
+
+ case 4:
+ if (strcmp(argv[1], "tftp") == 0) {
+ copy_filename(BootFile, argv[2], sizeof (BootFile));
+ load_addr = simple_strtoul(argv[3], NULL, 16);
+
+ if (NetLoop(bd, TFTP) == 0) {
+ printf("tftp transfer failed - aborting fgpa load\n");
+ return;
+ }
+
+ if (NetBootFileXferSize == 0) {
+ printf("can't determine file size - aborting fpga load\n");
+ return;
+ }
+
+ printf("File transfer succeeded - beginning fpga load...");
+
+ result = fpga_load(bd, 0, (uchar *)load_addr, NetBootFileXferSize);
+
+ if (result == LOAD_SUCCESS)
+ printf("SUCCEEDED\n");
+ else if (result == LOAD_FAIL_NOINIT)
+ printf("FAILED (no INIT)\n");
+ else
+ printf("FAILED (no DONE)\n");
+ return;
+ }
+ /* fall through ... */
+
+ case 5:
+ if (strcmp(argv[1], "load") == 0) {
+ if (argc == 5) {
+ if (strcmp(argv[2], "main") == 0)
+ mezz = 0;
+ else if (strcmp(argv[2], "mezz") == 0)
+ mezz = 1;
+ else {
+ printf("FPGA type must be either `main' or `mezz'\n");
+ return;
+ }
+ arg = 3;
+ }
+ else {
+ mezz = 0;
+ arg = 2;
+ }
+ addr = (uchar *)simple_strtoul(argv[arg++], NULL, 16);
+ size = (ulong)simple_strtoul(argv[arg], NULL, 16);
+
+ result = fpga_load(bd, mezz, addr, size);
+
+ if (result == LOAD_SUCCESS)
+ printf("SUCCEEDED\n");
+ else if (result == LOAD_FAIL_NOINIT)
+ printf("FAILED (no INIT)\n");
+ else
+ printf("FAILED (no DONE)\n");
+ return;
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ printf("Usage:\n%s\n", cmdtp->usage);
+ return;
+}
+
+/* ------------------------------------------------------------------------- */
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * hacked for HYMOD FPGA support by Murray.Jensen@cmst.csiro.au, 29-Jan-01
+ */
+
+/*
+ * Hymod FPGA command support
+ */
+#ifndef _CMD_FPGA_H
+#define _CMD_FPGA_H
+
+#include <ppcboot.h>
+#include <command.h>
+
+#if defined(CONFIG_HYMOD)
+
+#define CMD_TBL_FPGA MK_CMD_TBL_ENTRY( \
+ "fpga", 4, 6, 1, do_fpga, \
+ "fpga - FPGA sub-system\n", \
+ "load [type] addr size\n" \
+ " - write the configuration data at memory address `addr',\n" \
+ " size `size' bytes, into the FPGA of type `type' (either\n" \
+ " `main' or `mezz', default `main'). e.g.\n" \
+ " `fpga load 100000 7d8f'\n" \
+ " loads the main FPGA with config data at address 100000\n" \
+ " HEX, size 7d8f HEX (32143 DEC) bytes\n" \
+ "fpga store addr\n" \
+ " - read configuration data from the main FPGA (the mezz\n" \
+ " FPGA is write-only), into address `addr'. There must be\n" \
+ " enough memory available at `addr' to hold all the config\n"\
+ " data - the size of which is determined by VC:???\n" \
+ "fpga info\n" \
+ " - print information about the Hymod FPGA, namely the\n" \
+ " memory addresses at which the four FPGA local bus\n" \
+ " address spaces appear in the physical address space\n" \
+),
+
+void do_fpga (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
+
+#else
+#define CMD_TBL_FPGA
+#endif
+
+#endif /* _CMD_FPGA_H */
cmd_ide.o cmd_mem.o cmd_net.o \
cmd_nvedit.o cmd_pcmcia.o cmd_reginfo.o \
s_record.o dlmalloc.o \
- kgdb.o console.o lists.o devices.o flash.o cmd_i2c.o
+ kgdb.o console.o lists.o devices.o flash.o cmd_i2c.o cmd_immap.o
OBJS = $(AOBJS) $(COBJS)
/* set up serial port */
serial_init (idata->cpu_clk, baudrate);
+ idata->have_console = 1;
+
/* Initialize the console (before the relocation) */
console_init_f ();
if (bd_ptr->bi_mon_fnc->getc != serial_getc)
{
- if (tstc())
+ if (ctrlc())
{
- switch (getc()){
- case '\0':
- case 0x03: /* ^C - Control C */
- return (-1);
- }
+ return (-1);
}
}
}
#ifdef CONFIG_MPC8260
i2c_init(50000, 0xfe); /* use all one's as slave address */
#else
- i2c_init(50000);
+ i2c_init ();
#endif
printf("DONE\n");
return;
#ifdef CONFIG_MPC8260
i2c_init(speed, 0xfe); /* use all one's as slave address */
#else
- i2c_init(speed);
+ i2c_init ();
#endif
printf("DONE\n");
return;
#undef IDE_DEBUG
#ifdef IDE_DEBUG
-#define PRINTF(fmt,args...) do { \
- printf (fmt ,##args); \
- } while (0)
+#define PRINTF(fmt,args...) printf (fmt ,##args)
#else
#define PRINTF(fmt,args...)
#endif
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * MPC8xx/MPC8260 Internal Memory Map Functions
+ */
+
+#include <ppcboot.h>
+#include <command.h>
+#include <cmd_immap.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_IMMAP) && \
+ (defined(CONFIG_8xx) || defined(CONFIG_8260))
+
+#if defined(CONFIG_8xx)
+#include <asm/8xx_immap.h>
+#include <commproc.h>
+#elif defined(CONFIG_8260)
+#include <asm/immap_8260.h>
+#include <asm/cpm_8260.h>
+#endif
+
+static void
+unimplemented(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+{
+ printf("Sorry, but the '%s' command has not been implemented\n",
+ cmdtp->name);
+}
+
+void
+do_siuinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+#if defined(CONFIG_8xx)
+ volatile sysconf8xx_t *sc = &immap->im_siu_conf;
+#elif defined(CONFIG_8260)
+ volatile sysconf8260_t *sc = &immap->im_siu_conf;
+#endif
+
+ printf("SIUMCR= %08x SYPCR = %08x\n", sc->sc_siumcr, sc->sc_sypcr);
+#if defined(CONFIG_8xx)
+ printf("SWT = %08x\n", sc->sc_swt);
+ printf("SIPEND= %08x SIMASK= %08x\n", sc->sc_sipend, sc->sc_simask);
+ printf("SIEL = %08x SIVEC = %08x\n", sc->sc_siel, sc->sc_sivec);
+ printf("TESR = %08x SDCR = %08x\n", sc->sc_tesr, sc->sc_sdcr);
+#elif defined(CONFIG_8260)
+ printf("BCR = %08x\n", sc->sc_bcr);
+ printf("P_ACR = %02x P_ALRH= %08x P_ALRL= %08x\n",
+ sc->sc_ppc_acr, sc->sc_ppc_alrh, sc->sc_ppc_alrl);
+ printf("L_ACR = %02x L_ALRH= %08x L_ALRL= %08x\n",
+ sc->sc_lcl_acr, sc->sc_lcl_alrh, sc->sc_lcl_alrl);
+ printf("PTESR1= %08x PTESR2= %08x\n", sc->sc_tescr1, sc->sc_tescr2);
+ printf("LTESR1= %08x LTESR2= %08x\n", sc->sc_ltescr1, sc->sc_ltescr2);
+ printf("PDTEA = %08x PDTEM = %02x\n", sc->sc_pdtea, sc->sc_pdtem);
+ printf("LDTEA = %08x LDTEM = %02x\n", sc->sc_ldtea, sc->sc_ldtem);
+#endif
+}
+
+void
+do_memcinfo(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+#if defined(CONFIG_8xx)
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+ int nbanks = 8;
+#elif defined(CONFIG_8260)
+ volatile memctl8260_t *memctl = &immap->im_memctl;
+ int nbanks = 12;
+#endif
+ volatile uint *p = &memctl->memc_br0;
+ int i;
+
+ for (i = 0; i < nbanks; i++, p += 2)
+ if (i < 10)
+ printf("BR%d = %08x OR%d = %08x\n", i, p[0], i, p[1]);
+ else
+ printf("BR%d = %08x OR%d = %08x\n", i, p[0], i, p[1]);
+
+ printf("MAR = %08x", memctl->memc_mar);
+#if defined(CONFIG_8xx)
+ printf(" MCR = %08x\n", memctl->memc_mcr);
+#elif defined(CONFIG_8260)
+ printf("\n");
+#endif
+ printf("MAMR = %08x MBMR = %08x",
+ memctl->memc_mamr, memctl->memc_mbmr);
+#if defined(CONFIG_8xx)
+ printf("\nMSTAT = %04x\n", memctl->memc_mstat);
+#elif defined(CONFIG_8260)
+ printf(" MCMR = %08x\n", memctl->memc_mcmr);
+#endif
+ printf("MPTPR = %04x MDR = %08x\n",
+ memctl->memc_mptpr, memctl->memc_mdr);
+#if defined(CONFIG_8260)
+ printf("PSDMR = %08x LSDMR = %08x\n",
+ memctl->memc_psdmr, memctl->memc_lsdmr);
+ printf("PURT = %02x PSRT = %02x\n",
+ memctl->memc_purt, memctl->memc_psrt);
+ printf("LURT = %02x LSRT = %02x\n",
+ memctl->memc_lurt, memctl->memc_lsrt);
+ printf("IMMR = %08x\n", memctl->memc_immr);
+#endif
+}
+
+void
+do_sitinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+{
+ unimplemented(cmdtp, bd, flag, argc, argv);
+}
+
+#ifdef CONFIG_8260
+void
+do_icinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+{
+ unimplemented(cmdtp, bd, flag, argc, argv);
+}
+#endif
+
+void
+do_carinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+{
+ unimplemented(cmdtp, bd, flag, argc, argv);
+}
+
+static int counter;
+
+static void
+header(void)
+{
+ char *data = "\
+ -------------------------------- --------------------------------\
+ 00000000001111111111222222222233 00000000001111111111222222222233\
+ 01234567890123456789012345678901 01234567890123456789012345678901\
+ -------------------------------- --------------------------------\
+ ";
+ int i;
+
+ if (counter % 2)
+ putc('\n');
+ counter = 0;
+
+ for (i = 0; i < 4; i++, data += 79)
+ printf("%.79s\n", data);
+}
+
+static void
+binary(char *label, uint value, int nbits)
+{
+ uint mask = 1 << (nbits - 1);
+ int i, second = (counter++ % 2);
+
+ if (second)
+ putc(' ');
+ puts(label);
+ for (i = 32 + 1; i != nbits; i--)
+ putc(' ');
+
+ while (mask != 0) {
+ if (value & mask)
+ putc('1');
+ else
+ putc('0');
+ mask >>= 1;
+ }
+
+ if (second)
+ putc('\n');
+}
+
+#if defined(CONFIG_8xx)
+#define PA_NBITS 16
+#define PA_NB_ODR 8
+#define PB_NBITS 18
+#define PB_NB_ODR 16
+#define PC_NBITS 12
+#define PD_NBITS 13
+#elif defined(CONFIG_8260)
+#define PA_NBITS 32
+#define PA_NB_ODR 32
+#define PB_NBITS 28
+#define PB_NB_ODR 28
+#define PC_NBITS 32
+#define PD_NBITS 28
+#endif
+
+void
+do_iopinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+#if defined(CONFIG_8xx)
+ volatile iop8xx_t *iop = &immap->im_ioport;
+ volatile ushort *l, *r;
+#elif defined(CONFIG_8260)
+ volatile iop8260_t *iop = &immap->im_ioport;
+ volatile uint *l, *r;
+#endif
+ volatile uint *R;
+
+ counter = 0;
+ header();
+
+ /*
+ * Ports A & B
+ */
+
+#if defined(CONFIG_8xx)
+ l = &iop->iop_padir;
+ R = &immap->im_cpm.cp_pbdir;
+#elif defined(CONFIG_8260)
+ l = &iop->iop_pdira;
+ R = &iop->iop_pdirb;
+#endif
+ binary("PA_DIR", *l++, PA_NBITS); binary("PB_DIR", *R++, PB_NBITS);
+ binary("PA_PAR", *l++, PA_NBITS); binary("PB_PAR", *R++, PB_NBITS);
+#if defined(CONFIG_8260)
+ binary("PA_SOR", *l++, PA_NBITS); binary("PB_SOR", *R++, PB_NBITS);
+#endif
+ binary("PA_ODR", *l++, PA_NB_ODR); binary("PB_ODR", *R++, PB_NB_ODR);
+ binary("PA_DAT", *l++, PA_NBITS); binary("PB_DAT", *R++, PB_NBITS);
+
+ header();
+
+ /*
+ * Ports C & D
+ */
+
+#if defined(CONFIG_8xx)
+ l = &iop->iop_pcdir;
+ r = &iop->iop_pddir;
+#elif defined(CONFIG_8260)
+ l = &iop->iop_pdirc;
+ r = &iop->iop_pdird;
+#endif
+ binary("PC_DIR", *l++, PC_NBITS); binary("PD_DIR", *r++, PD_NBITS);
+ binary("PC_PAR", *l++, PC_NBITS); binary("PD_PAR", *r++, PD_NBITS);
+#if defined(CONFIG_8xx)
+ binary("PC_SO ", *l++, PC_NBITS); binary(" ", 0, 0); r++;
+#elif defined(CONFIG_8260)
+ binary("PC_SOR", *l++, PC_NBITS); binary("PD_SOR", *r++, PD_NBITS);
+ binary("PC_ODR", *l++, PC_NBITS); binary("PD_ODR", *r++, PD_NBITS);
+#endif
+ binary("PC_DAT", *l++, PC_NBITS); binary("PD_DAT", *r++, PD_NBITS);
+#if defined(CONFIG_8xx)
+ binary("PC_INT", *l++, PC_NBITS);
+#endif
+
+ header();
+}
+
+void
+do_dmainfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+{
+ unimplemented(cmdtp, bd, flag, argc, argv);
+}
+
+void
+do_fccinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+{
+ unimplemented(cmdtp, bd, flag, argc, argv);
+}
+
+static void
+prbrg(int n, uint val)
+{
+ uint extc = (val >> 14) & 3;
+ uint cd = (val & CPM_BRG_CD_MASK) >> 1;
+ uint div16 = (val & CPM_BRG_DIV16) != 0;
+ /* Pointer to initial global data area */
+ init_data_t *idata = (init_data_t *)(CFG_INIT_RAM_ADDR + CFG_INIT_DATA_OFFSET);
+#if defined(CONFIG_8xx)
+ ulong clock = idata->cpu_clk;
+#elif defined(CONFIG_8260)
+ ulong clock = idata->brg_clk;
+#endif
+
+ printf("BRG%d:", n);
+
+ if (val & CPM_BRG_RST)
+ puts(" RESET");
+ else
+ puts(" ");
+
+ if (val & CPM_BRG_EN)
+ puts(" ENABLED");
+ else
+ puts(" DISABLED");
+
+ printf(" EXTC=%d", extc);
+
+ if (val & CPM_BRG_ATB)
+ puts(" ATB");
+ else
+ puts(" ");
+
+ printf(" DIVIDER=%4d", cd);
+ if (extc == 0 && cd != 0) {
+ uint baudrate;
+
+ if (div16)
+ baudrate = (clock / 16) / (cd + 1);
+ else
+ baudrate = clock / (cd + 1);
+
+ printf("=%6d bps", baudrate);
+ }
+ else
+ puts(" ");
+
+ if (val & CPM_BRG_DIV16)
+ puts(" DIV16");
+ else
+ puts(" ");
+
+ putc('\n');
+}
+
+void
+do_brginfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+#if defined(CONFIG_8xx)
+ volatile cpm8xx_t *cp = &immap->im_cpm;
+ volatile uint *p = &cp->cp_brgc1;
+#elif defined(CONFIG_8260)
+ volatile uint *p = &immap->im_brgc1;
+#endif
+ int i = 1;
+
+ while (i <= 4)
+ prbrg(i++, *p++);
+
+#if defined(CONFIG_8260)
+ p = &immap->im_brgc5;
+ while (i <= 8)
+ prbrg(i++, *p++);
+#endif
+}
+
+void
+do_i2cinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+{
+ unimplemented(cmdtp, bd, flag, argc, argv);
+}
+
+void
+do_sccinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+{
+ unimplemented(cmdtp, bd, flag, argc, argv);
+}
+
+void
+do_smcinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+{
+ unimplemented(cmdtp, bd, flag, argc, argv);
+}
+
+void
+do_spiinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+{
+ unimplemented(cmdtp, bd, flag, argc, argv);
+}
+
+void
+do_muxinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+{
+ unimplemented(cmdtp, bd, flag, argc, argv);
+}
+
+void
+do_siinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+{
+ unimplemented(cmdtp, bd, flag, argc, argv);
+}
+
+void
+do_mccinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+{
+ unimplemented(cmdtp, bd, flag, argc, argv);
+}
+
+#endif /* CFG_CMD_IMMAP && (CONFIG_8xx || CONFIG_8260) */
int memval;
for (;;) {
- if (tstc()) {
- switch (getc()) {
- case '\0':
- case 0x03: /* ^C - Control C */
- return;
- }
+ if (ctrlc()) {
+ return;
}
memaddr = (uint *)CFG_MEMTEST_START;
putc(get_env_char(k));
putc ('\n');
- if (tstc()) {
- getc ();
+ if (ctrlc()) {
printf ("\n ** Abort\n");
return;
}
#include <cmd_eeprom.h>
#include <cmd_i2c.h>
+#include <cmd_immap.h>
+#ifdef CONFIG_HYMOD
+#include <../board/hymod/cmd_fpga.h>
+#endif
/*
* HELP command
for (cmdtp=&cmd_tbl[0]; cmdtp->name; cmdtp++) {
/* allow user abort */
- if (tstc())
+ if (ctrlc())
return;
if (cmdtp->usage == NULL)
CMD_TBL_RESET
CMD_TBL_KGDB
CMD_TBL_I2C
+#ifdef CONFIG_HYMOD
+ CMD_TBL_FPGA
+#endif
CMD_TBL_ECHO
+ CMD_TBL_SIUINFO
+ CMD_TBL_MEMCINFO
+ CMD_TBL_SITINFO
+ CMD_TBL_ICINFO
+ CMD_TBL_CARINFO
+ CMD_TBL_IOPINFO
+ CMD_TBL_DMAINFO
+ CMD_TBL_FCCINFO
+ CMD_TBL_BRGINFO
+ CMD_TBL_I2CINFO
+ CMD_TBL_SCCINFO
+ CMD_TBL_SMCINFO
+ CMD_TBL_SPIINFO
+ CMD_TBL_MUXINFO
+ CMD_TBL_SIINFO
+ CMD_TBL_MCCINFO
CMD_TBL_VERS
CMD_TBL_HELP
CMD_TBL_QUES
puts (printbuffer);
}
+// test if ctrl-c was pressed.
+int
+ctrlc(void)
+{
+ init_data_t *idata =
+ (init_data_t *)(CFG_INIT_RAM_ADDR + CFG_INIT_DATA_OFFSET);
+
+ if (idata->have_console) {
+ if (tstc()) {
+ switch (getc()) {
+ case 0x03: /* ^C - Control C */
+ return 1;
+ default:
+ }
+ }
+ }
+ return 0;
+}
+
//** PPCBOOT INIT FUNCTIONS *************************************************
int console_assign (int file, char *devname)
if (div16)
*bp |= CPM_BRG_DIV16;
}
+
+/* This function is used to set baud rate generators using an external
+ * clock source and 16x oversampling.
+ */
+
+void
+m8260_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel)
+{
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile uint *bp;
+
+ if (brg < 4) {
+ bp = (uint *)&immr->im_brgc1;
+ }
+ else {
+ bp = (uint *)&immr->im_brgc5;
+ brg -= 4;
+ }
+ bp += brg;
+ *bp = ((((((extclk/16)+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN;
+ if (pinsel == 0)
+ *bp |= CPM_BRG_EXTC_CLK3_9;
+ else
+ *bp |= CPM_BRG_EXTC_CLK5_15;
+}
/* ------------------------------------------------------------------------- */
/* configures a UPM by writing into the UPM RAM array */
-/* uses bank 11 and physical address 0x80000000 */
+/* uses bank 11 and a dummy physical address (=BRx_BA_MSK) */
/* NOTE: the physical address chosen must not overlap into any other area */
/* mapped by the memory controller because bank 11 has the lowest priority */
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
- volatile uchar *dummy = (uchar *)0x80000000;
+ volatile uchar *dummy = (uchar *)BRx_BA_MSK; /* set all BA bits */
uint i;
/* first set up bank 11 to reference the correct UPM at a dummy address */
/* tx/rx timeout (we need the i2c early, so we don't use get_timer()) */
#define TOUT_LOOP 1000000
-#define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */
#define NUM_RX_BDS 4
#define NUM_TX_BDS 4
#define MAX_TX_SPACE 256
txbd = ((I2C_BD*)state->txbd) - 1;
PRINTD(("[I2C] Transmitting...(txbd=0x%08lx)\n", (ulong)txbd));
while((txbd->status & BD_SC_READY) && (j++ < TOUT_LOOP)) {
- if (tstc()) {
- switch (getc()) {
- case '\0':
- case 0x03: /* ^C - Control C */
- return (-1);
- }
- }
+ if (ctrlc())
+ return (-1);
__asm__ __volatile__ ("eieio");
}
}
rxbd = ((I2C_BD*)state->rxbd) - 1;
PRINTD(("[I2C] Receiving...(rxbd=0x%08lx)\n", (ulong)rxbd));
while((rxbd->status & BD_SC_EMPTY) && (j++ < TOUT_LOOP)) {
- if (tstc()) {
- switch (getc()) {
- case '\0':
- case 0x03: /* ^C - Control C */
- return (-1);
- }
- }
+ if (ctrlc())
+ return (-1);
__asm__ __volatile__ ("eieio");
}
}
void
serial_setbrg (ulong cpu_clock, int baudrate)
{
+#if defined(CONFIG_CONS_USE_EXTC)
+ m8260_cpm_extcbrg(SCC_INDEX, baudrate,
+ CONFIG_CONS_EXTC_RATE, CONFIG_CONS_EXTC_PINSEL);
+#else
m8260_cpm_setbrg(SCC_INDEX, baudrate);
+#endif
}
void
/* Set up the baud rate generator.
*/
+#if defined(CONFIG_KGDB_USE_EXTC)
+ m8260_cpm_extcbrg(KGDB_SCC_INDEX, speed,
+ CONFIG_KGDB_EXTC_RATE, CONFIG_KGDB_EXTC_PINSEL);
+#else
m8260_cpm_setbrg(KGDB_SCC_INDEX, speed);
+#endif
/* Allocate space for two buffer descriptors in the DP ram.
* damm: allocating space after the two buffers for rx/tx data
void
serial_setbrg (ulong cpu_clock, int baudrate)
{
+#if defined(CONFIG_CONS_USE_EXTC)
+ m8260_cpm_extcbrg(SMC_INDEX, baudrate,
+ CONFIG_CONS_EXTC_RATE, CONFIG_CONS_EXTC_PINSEL);
+#else
m8260_cpm_setbrg(SMC_INDEX, baudrate);
+#endif
}
void
/* Set up the baud rate generator.
*/
+#if defined(CONFIG_KGDB_USE_EXTC)
+ m8260_cpm_extcbrg(KGDB_SMC_INDEX, speed,
+ CONFIG_KGDB_EXTC_RATE, CONFIG_KGDB_EXTC_PINSEL);
+#else
m8260_cpm_setbrg(KGDB_SMC_INDEX, speed);
+#endif
/* Make the first buffer the only buffer.
*/
uint m8260_cpm_hostalloc(uint size, uint align);
void m8260_cpm_setbrg(uint brg, uint rate);
void m8260_cpm_fastbrg(uint brg, uint rate, int div16);
+void m8260_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel);
/* Buffer descriptors used by many of the CPM protocols.
*/
--- /dev/null
+#ifndef _ASM_HYMOD_H_
+#define _ASM_HYMOD_H_
+
+#include <linux/types.h>
+#include <asm/iopin_8260.h>
+
+/*
+ * hymod configuration data - passed by boot code via the board information
+ * structure (only ppcboot has support for this at the moment)
+ *
+ * there are three types of data passed up from the boot monitor. the first
+ * (type hymod_prom_t) is the eeprom data that was read off both the main
+ * (or mother) board and the mezzanine board (if any). this data defines how
+ * many fpgas are on each board, and their types (among other things). the
+ * second type of data (type fpga_mmap_t, one per fpga) defines where in the
+ * physical address space the various fpga access regions have been mapped by
+ * the boot rom. the third type of data (type fpga_iopins_t, one per fpga)
+ * defines which 8260 io port pins are connected to the various signals
+ * required to program a hymod fpga.
+ */
+
+#define MAX_FPGA 4 /* max fpgas on any hymod board */
+
+/*
+ * this defines the layout of a date field in the hymod serial eeprom
+ */
+typedef
+ struct {
+ ulong year:12;
+ ulong month:4;
+ ulong day:5;
+ ulong :11;
+ }
+hymod_date_t;
+
+/*
+ * this defines the contents of the serial prom that exists on every
+ * hymod board, including mezzanine boards (the serial prom will be
+ * faked for early development boards that don't have one)
+ */
+typedef
+ struct {
+ ulong crc; /* crc32 checksum of prom contents */
+ hymod_date_t date; /* manufacture date */
+ ulong serno; /* serial number */
+ ushort type; /* board type */
+ ushort rev; /* board revision */
+ ushort ver; /* version of prom contents */
+ ushort nfpga; /* how many fpgas on this board */
+ ushort ftype[MAX_FPGA]; /* FPGA types */
+ }
+hymod_prom_t;
+
+/* hymod board types */
+#define HYMOD_BDTYPE_IO 0 /* I/O board */
+#define HYMOD_BDTYPE_CLP 1 /* CLP board */
+#define HYMOD_BDTYPE_INPUT 2 /* INPUT board */
+#define HYMOD_BDTYPE_DISPLAY 3 /* DISPLAY board */
+
+/* hymod FPGA types */
+#define HYMOD_FPGATYPE_XCV300E 0 /* Xilinx XCV300E */
+
+/*
+ * this defines a region in the processor's physical address space
+ */
+typedef
+ struct {
+ ulong exists:1; /* 1 if the region exists, 0 if not */
+ ulong size:31; /* size in bytes */
+ ulong base; /* base address */
+ }
+fpga_prgn_t;
+
+/*
+ * this defines where the different fpga access methods are mapped
+ * into the physical address space of the processor for an fpga
+ */
+typedef
+ struct {
+ fpga_prgn_t prog; /* program access region */
+ fpga_prgn_t reg; /* register access region */
+ fpga_prgn_t port; /* port access region */
+ }
+fpga_mmap_t;
+
+/*
+ * this defines which 8260 i/o port pins are connected to the various
+ * signals required for programming a hymod fpga
+ */
+typedef
+ struct {
+ iopin_t prog_pin; /* assert for >= 300ns to program */
+ iopin_t init_pin; /* goes high when fpga is cleared */
+ iopin_t done_pin; /* goes high when program is done */
+ iopin_t enable_pin; /* some fpgas need enabling */
+ }
+fpga_iopins_t;
+
+/*
+ * this defines the configuration information of one hymod "system"
+ * (main board + possible mezzanine board)
+ */
+typedef
+ struct {
+ ulong flags; /* configuration flags */
+ hymod_prom_t main_prom; /* main board prom contents */
+ fpga_mmap_t main_mmap[MAX_FPGA];/* memory map of main board fpga(s) */
+ fpga_iopins_t main_iopins[MAX_FPGA];/* io pins for main board fpga(s) */
+ hymod_prom_t mezz_prom; /* mezzanine prom contents */
+ fpga_mmap_t mezz_mmap[MAX_FPGA];/* memory map of mezz fpga(s) */
+ fpga_iopins_t mezz_iopins[MAX_FPGA];/* io pins for mezz board fpga(s) */
+ }
+hymod_conf_t;
+
+/* hymod configuration flags */
+#define HYMOD_FLAG_MAINVALID 0x0001 /* main prom data and mmap is valid */
+#define HYMOD_FLAG_MEZZVALID 0x0002 /* mezz prom data and mmap is valid */
+
+#endif /* _ASM_HYMOD_H_ */
--- /dev/null
+/*
+ * MPC8260 I/O port pin manipulation functions
+ */
+
+#ifndef _ASM_IOPIN_8260_H_
+#define _ASM_IOPIN_8260_H_
+
+#include <linux/types.h>
+#include <asm/immap_8260.h>
+
+typedef
+ struct {
+ u_char port:2; /* port number (A=0, B=1, C=2, D=3) */
+ u_char pin:5; /* port pin (0-31) */
+ u_char flag:1; /* for whatever */
+ }
+iopin_t;
+
+#define IOPIN_PORTA 0
+#define IOPIN_PORTB 1
+#define IOPIN_PORTC 2
+#define IOPIN_PORTD 3
+
+extern __inline__ void
+iopin_set_high(iopin_t *iopin)
+{
+ volatile uint *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdata;
+ datp[iopin->port * 8] |= (1 << (31 - iopin->pin));
+}
+
+extern __inline__ void
+iopin_set_low(iopin_t *iopin)
+{
+ volatile uint *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdata;
+ datp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
+}
+
+extern __inline__ uint
+iopin_is_high(iopin_t *iopin)
+{
+ volatile uint *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdata;
+ return (datp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
+}
+
+extern __inline__ uint
+iopin_is_low(iopin_t *iopin)
+{
+ volatile uint *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdata;
+ return ((datp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
+}
+
+extern __inline__ void
+iopin_set_out(iopin_t *iopin)
+{
+ volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdira;
+ dirp[iopin->port * 8] |= (1 << (31 - iopin->pin));
+}
+
+extern __inline__ void
+iopin_set_in(iopin_t *iopin)
+{
+ volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdira;
+ dirp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
+}
+
+extern __inline__ uint
+iopin_is_out(iopin_t *iopin)
+{
+ volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdira;
+ return (dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
+}
+
+extern __inline__ uint
+iopin_is_in(iopin_t *iopin)
+{
+ volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdira;
+ return ((dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
+}
+
+extern __inline__ void
+iopin_set_odr(iopin_t *iopin)
+{
+ volatile uint *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_podra;
+ odrp[iopin->port * 8] |= (1 << (31 - iopin->pin));
+}
+
+extern __inline__ void
+iopin_set_act(iopin_t *iopin)
+{
+ volatile uint *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_podra;
+ odrp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
+}
+
+extern __inline__ uint
+iopin_is_odr(iopin_t *iopin)
+{
+ volatile uint *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_podra;
+ return (odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
+}
+
+extern __inline__ uint
+iopin_is_act(iopin_t *iopin)
+{
+ volatile uint *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_podra;
+ return ((odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
+}
+
+extern __inline__ void
+iopin_set_ded(iopin_t *iopin)
+{
+ volatile uint *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_ppara;
+ parp[iopin->port * 8] |= (1 << (31 - iopin->pin));
+}
+
+extern __inline__ void
+iopin_set_gen(iopin_t *iopin)
+{
+ volatile uint *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_ppara;
+ parp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
+}
+
+extern __inline__ uint
+iopin_is_ded(iopin_t *iopin)
+{
+ volatile uint *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_ppara;
+ return (parp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
+}
+
+extern __inline__ uint
+iopin_is_gen(iopin_t *iopin)
+{
+ volatile uint *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_ppara;
+ return ((parp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
+}
+
+extern __inline__ void
+iopin_set_opt2(iopin_t *iopin)
+{
+ volatile uint *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_psora;
+ sorp[iopin->port * 8] |= (1 << (31 - iopin->pin));
+}
+
+extern __inline__ void
+iopin_set_opt1(iopin_t *iopin)
+{
+ volatile uint *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_psora;
+ sorp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
+}
+
+extern __inline__ uint
+iopin_is_opt2(iopin_t *iopin)
+{
+ volatile uint *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_psora;
+ return (sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
+}
+
+extern __inline__ uint
+iopin_is_opt1(iopin_t *iopin)
+{
+ volatile uint *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_psora;
+ return ((sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
+}
+
+#endif /* _ASM_IOPIN_8260_H_ */
#define CFG_CMD_ECHO 0x00080000 /* echo arguments */
#define CFG_CMD_I2C 0x00100000 /* I2C serial bus support */
#define CFG_CMD_REGINFO 0x00200000 /* Register dump */
+#define CFG_CMD_IMMAP 0x00400000 /* IMMR dump support */
#define CFG_CMD_ALL 0xFFFFFFFF /* ALL commands */
CFG_CMD_ASKENV | \
CFG_CMD_ECHO | \
CFG_CMD_I2C | \
- CFG_CMD_REGINFO )
+ CFG_CMD_REGINFO | \
+ CFG_CMD_IMMAP )
/* Default configuration
*/
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * PowerPC 8xx/8260 Internal Memory Map commands
+ */
+#ifndef _CMD_IMMAP_H
+#define _CMD_IMMAP_H
+
+#if (CONFIG_COMMANDS & CFG_CMD_IMMAP) && \
+ (defined(CONFIG_8xx) || defined(CONFIG_8260))
+
+#define CMD_TBL_SIUINFO MK_CMD_TBL_ENTRY( \
+ "siuinfo", 3, 1, 1, do_siuinfo, \
+ "siuinfo - print System Interface Unit (SIU) registers\n", \
+ NULL \
+),
+
+#define CMD_TBL_MEMCINFO MK_CMD_TBL_ENTRY( \
+ "memcinfo", 4, 1, 1, do_memcinfo, \
+ "memcinfo- print Memory Controller registers\n", \
+ NULL \
+),
+
+#define CMD_TBL_SITINFO MK_CMD_TBL_ENTRY( \
+ "sitinfo", 3, 1, 1, do_sitinfo, \
+ "sitinfo - print System Integration Timers (SIT) registers\n", \
+ NULL \
+),
+
+#ifdef CONFIG_8260
+#define CMD_TBL_ICINFO MK_CMD_TBL_ENTRY( \
+ "icinfo", 2, 1, 1, do_icinfo, \
+ "icinfo - print Interrupt Controller registers\n", \
+ NULL \
+),
+#endif
+
+#define CMD_TBL_CARINFO MK_CMD_TBL_ENTRY( \
+ "carinfo", 3, 1, 1, do_carinfo, \
+ "carinfo - print Clocks and Reset registers\n", \
+ NULL \
+),
+
+#define CMD_TBL_IOPINFO MK_CMD_TBL_ENTRY( \
+ "iopinfo", 3, 1, 1, do_iopinfo, \
+ "iopinfo - print I/O Port registers\n", \
+ NULL \
+),
+
+#define CMD_TBL_DMAINFO MK_CMD_TBL_ENTRY( \
+ "dmainfo", 3, 1, 1, do_dmainfo, \
+ "dmainfo - print SDMA/IDMA registers\n", \
+ NULL \
+),
+
+#define CMD_TBL_FCCINFO MK_CMD_TBL_ENTRY( \
+ "fccinfo", 3, 1, 1, do_fccinfo, \
+ "fccinfo - print FCC registers\n", \
+ NULL \
+),
+
+#define CMD_TBL_BRGINFO MK_CMD_TBL_ENTRY( \
+ "brginfo", 3, 1, 1, do_brginfo, \
+ "brginfo - print Baud Rate Generator (BRG) registers\n", \
+ NULL \
+),
+
+#define CMD_TBL_I2CINFO MK_CMD_TBL_ENTRY( \
+ "i2cinfo", 4, 1, 1, do_i2cinfo, \
+ "i2cinfo - print I2C registers\n", \
+ NULL \
+),
+
+#define CMD_TBL_SCCINFO MK_CMD_TBL_ENTRY( \
+ "sccinfo", 3, 1, 1, do_sccinfo, \
+ "sccinfo - print SCC registers\n", \
+ NULL \
+),
+
+#define CMD_TBL_SMCINFO MK_CMD_TBL_ENTRY( \
+ "smcinfo", 3, 1, 1, do_smcinfo, \
+ "smcinfo - print SMC registers\n", \
+ NULL \
+),
+
+#define CMD_TBL_SPIINFO MK_CMD_TBL_ENTRY( \
+ "spiinfo", 3, 1, 1, do_spiinfo, \
+ "spiinfo - print Serial Peripheral Interface (SPI) registers\n",\
+ NULL \
+),
+
+#define CMD_TBL_MUXINFO MK_CMD_TBL_ENTRY( \
+ "muxinfo", 3, 1, 1, do_muxinfo, \
+ "muxinfo - print CPM Multiplexing registers\n", \
+ NULL \
+),
+
+#define CMD_TBL_SIINFO MK_CMD_TBL_ENTRY( \
+ "siinfo", 3, 1, 1, do_siinfo, \
+ "siinfo - print Serial Interface (SI) registers\n", \
+ NULL \
+),
+
+#define CMD_TBL_MCCINFO MK_CMD_TBL_ENTRY( \
+ "mccinfo", 3, 1, 1, do_mccinfo, \
+ "mccinfo - print MCC registers\n", \
+ NULL \
+),
+
+void do_siuinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
+void do_memcinfo(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
+void do_sitinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
+#ifdef CONFIG_8260
+void do_icinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
+#endif
+void do_carinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
+void do_iopinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
+void do_dmainfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
+void do_fccinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
+void do_brginfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
+void do_i2cinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
+void do_sccinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
+void do_smcinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
+void do_spiinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
+void do_muxinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
+void do_siinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
+void do_mccinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
+
+#else
+
+#define CMD_TBL_SIUINFO
+#define CMD_TBL_MEMCINFO
+#define CMD_TBL_SITINFO
+#define CMD_TBL_ICINFO
+#define CMD_TBL_CARINFO
+#define CMD_TBL_IOPINFO
+#define CMD_TBL_DMAINFO
+#define CMD_TBL_FCCINFO
+#define CMD_TBL_BRGINFO
+#define CMD_TBL_I2CINFO
+#define CMD_TBL_SCCINFO
+#define CMD_TBL_SMCINFO
+#define CMD_TBL_SPIINFO
+#define CMD_TBL_MUXINFO
+#define CMD_TBL_SIINFO
+#define CMD_TBL_MCCINFO
+
+#endif /* CFG_CMD_IMMAP && (CONFIG_8xx || CONFIG_8260) */
+
+#endif /* _CMD_IMMAP_H */
*/
#define CONFIG_CONS_ON_SMC /* define if console on SMC */
#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
-#undef CONFIG_CONS_NONE /* define if console on neither */
-#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
+#undef CONFIG_CONS_NONE /* define if console on something else*/
+#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
+#undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
+#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */
+#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
/*
* select ethernet configuration
* defined elsewhere (as for the console), or CFG_CMD_NET must be removed
* from CONFIG_COMMANDS to remove support for networking.
*/
-#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */
-#undef CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */
-#define CONFIG_ETHER_NONE /* define if ethernet on neither */
-#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
+#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
+#undef CONFIG_ETHER_ON_FCC /* define if ether on FCC */
+#define CONFIG_ETHER_NONE /* define if ether on something else */
+#define CONFIG_ETHER_INDEX 1 /* which channel for ether */
/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
#define CONFIG_8260_CLKIN 66666666 /* in Hz */
-#ifdef CONFIG_CONS_NONE
+#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
#define CONFIG_BAUDRATE 230400
#else
#define CONFIG_BAUDRATE 9600
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
#undef CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
-#undef CONFIG_KGDB_NONE /* define if kgdb on neither */
-#define CONFIG_KGDB_INDEX 2 /* which SMC/SCC channel for kgdb */
-#ifdef CONFIG_KGDB_NONE
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#else
-#define CONFIG_KGDB_BAUDRATE 9600 /* speed to run kgdb serial port */
-#endif
+#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
+#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
+#define CONFIG_KGDB_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
+#define CONFIG_KGDB_EXTC_RATE 3686400 /* serial ext clk rate in Hz */
+#define CONFIG_KGDB_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
+# if defined(CONFIG_KGDB_NONE) || defined(CONFIG_KGDB_USE_EXTC)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port at */
+# else
+#define CONFIG_KGDB_BAUDRATE 9600 /* speed to run kgdb serial port at */
+# endif
#endif
-#undef CONFIG_WATCHDOG /* turn on platform specific watchdog */
+#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
/*
* Miscellaneous configurable options
#define CONFIG_BAUDRATE 230400
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_KGDB) & ~CFG_CMD_NET)
+#define CONFIG_I2C
+
+#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_KGDB | CFG_CMD_I2C) & ~CFG_CMD_NET)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CFG_ALLOC_DPRAM
+
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
*/
#undef CONFIG_CONS_ON_SMC /* define if console on SMC */
#define CONFIG_CONS_ON_SCC /* define if console on SCC */
-#undef CONFIG_CONS_NONE /* define if console on neither */
-#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
+#undef CONFIG_CONS_NONE /* define if console on something else*/
+#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
+#define CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
+#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */
+#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
/*
* select ethernet configuration
* defined elsewhere (as for the console), or CFG_CMD_NET must be removed
* from CONFIG_COMMANDS to remove support for networking.
*/
-#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */
-#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */
-#undef CONFIG_ETHER_NONE /* define if ethernet on neither */
-#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
+#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
+#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
+#undef CONFIG_ETHER_NONE /* define if ether on something else */
+#define CONFIG_ETHER_INDEX 1 /* which channel for ether */
/* other options */
#define CONFIG_I2C 1 /* To enable I2C support */
#define CONFIG_8260_CLKIN 66666666 /* in Hz */
#endif
+#if defined(CONFIG_CONS_USE_EXTC)
+#define CONFIG_BAUDRATE 230400
+#else
#define CONFIG_BAUDRATE 9600
+#endif
#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \
CFG_CMD_IDE | \
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
-#undef CONFIG_KGDB_NONE /* define if kgdb on neither */
-#define CONFIG_KGDB_INDEX 2 /* which SMC/SCC channel for kgdb */
-#define CONFIG_KGDB_BAUDRATE 9600 /* speed to run kgdb serial port */
+#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
+#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
+#define CONFIG_KGDB_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
+#define CONFIG_KGDB_EXTC_RATE 3686400 /* serial ext clk rate in Hz */
+#define CONFIG_KGDB_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
+# if defined(CONFIG_KGDB_USE_EXTC)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port at */
+# else
+#define CONFIG_KGDB_BAUDRATE 9600 /* speed to run kgdb serial port at */
+# endif
#endif
-#undef CONFIG_WATCHDOG /* turn off platform specific watchdog */
+#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
/*
* Miscellaneous configurable options
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 8 /* max number of command args */
+#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
-#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
#define CFG_HYMOD_DBLEDS /* enable pretty pattern on the daughter board LEDs */
+#define CFG_HYMOD_NO_EEPROMS /* dev boards don't have eeproms */
/*
* Low Level Configuration Settings
#define CFG_SDRAM_BASE 0x00000000
#define CFG_FLASH_BASE TEXT_BASE
#define CFG_MONITOR_BASE TEXT_BASE
+#define CFG_FPGA_BASE 0x80000000
/*
* unfortunately, CFG_MONITOR_LEN must include the
* (very large i.e. 256kB) environment flash sector
#define CFG_MPTPR ((32<<MPTPR_PTP_SHIFT)&MPTPR_PTP_MSK)
#endif
+/*
+ * Banks 3,4,5 and 6 - FPGA access
+ *
+ * Quotes from the HYMOD IO Board Reference manual:
+ *
+ * "The IO Board is fitted with a Xilinx XCV300E main FPGA. Provision is made
+ * for configuring an optional FPGA on the mezzanine interface.
+ *
+ * Access to the FPGAs may be divided into several catagories:
+ *
+ * 1. Configuration
+ * 2. Register mode access
+ * 3. Port mode access
+ *
+ * The main FPGA is supported for modes 1, 2 and 3. The mezzanine FPGA can be
+ * configured only (mode 1). Consequently there are four access types.
+ *
+ * To improve interface performance and simplify software design, the four
+ * possible access types are separately mapped to different memory banks.
+ *
+ * All are accessed using the local bus."
+ *
+ * Device Mode Memory Bank Machine Port Size Access
+ *
+ * Main Configuration 3 UPMC 8bit R/W
+ * Main Register 4 GPCM 32bit R/W
+ * Main Port 5 UPMB 32bit R/W
+ * Mezzanine Configuration 6 UPMC 8bit W/O
+ *
+ * "Note that mezzanine mode 1 access is write-only."
+ */
+
+/* all the bank sizes must be a power of two, greater or equal to 32768 */
+#define FPGA_MAIN_CFG_BASE (CFG_FPGA_BASE)
+#define FPGA_MAIN_CFG_SIZE 32768
+#define FPGA_MAIN_REG_BASE (FPGA_MAIN_CFG_BASE + FPGA_MAIN_CFG_SIZE)
+#define FPGA_MAIN_REG_SIZE 32768
+#define FPGA_MAIN_PORT_BASE (FPGA_MAIN_REG_BASE + FPGA_MAIN_REG_SIZE)
+#define FPGA_MAIN_PORT_SIZE 32768
+#define FPGA_MEZZ_CFG_BASE (FPGA_MAIN_PORT_BASE + FPGA_MAIN_PORT_SIZE)
+#define FPGA_MEZZ_CFG_SIZE 32768
+
+/* 8 bit, read-write, UPMC */
+#define CFG_BR3_PRELIM (FPGA_MAIN_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V)
+/* up to 32Kbyte, burst inhibit */
+#define CFG_OR3_PRELIM (P2SZ_TO_AM(FPGA_MAIN_CFG_SIZE)|ORxU_BI)
+
+/* 32 bit, read-write, GPCM */
+#define CFG_BR4_PRELIM (FPGA_MAIN_REG_BASE|BRx_PS_32|BRx_MS_GPCM_L|BRx_V)
+/* up to 32Kbyte */
+#define CFG_OR4_PRELIM (P2SZ_TO_AM(FPGA_MAIN_REG_SIZE))
+
+/* 32 bit, read-write, UPMB */
+#define CFG_BR5_PRELIM (FPGA_MAIN_PORT_BASE|BRx_PS_32|BRx_MS_UPMB|BRx_V)
+/* up to 32Kbyte */
+#define CFG_OR5_PRELIM (P2SZ_TO_AM(FPGA_MAIN_PORT_SIZE)|ORxU_BI)
+
+/* 8 bit, write-only, UPMC */
+#define CFG_BR6_PRELIM (FPGA_MEZZ_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V)
+/* up to 32Kbyte, burst inhibit */
+#define CFG_OR6_PRELIM (P2SZ_TO_AM(FPGA_MEZZ_CFG_SIZE)|ORxU_BI)
+
+/*-----------------------------------------------------------------------
+ * MBMR - Machine B Mode 10-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_MBMR (MxMR_BSEL|MxMR_OP_NORM) /* XXX - needs more */
+
+/*-----------------------------------------------------------------------
+ * MCMR - Machine C Mode 10-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_MCMR (MxMR_BSEL|MxMR_DSx_2_CYCL) /* XXX - needs more */
+
+/*
+ * FPGA I/O Port/Bit information
+ */
+
+#define FPGA_MAIN_PROG_PORT IOPIN_PORTA
+#define FPGA_MAIN_PROG_PIN 4 /* PA4 */
+#define FPGA_MAIN_INIT_PORT IOPIN_PORTA
+#define FPGA_MAIN_INIT_PIN 5 /* PA5 */
+#define FPGA_MAIN_DONE_PORT IOPIN_PORTA
+#define FPGA_MAIN_DONE_PIN 6 /* PA6 */
+
+#define FPGA_MEZZ_PROG_PORT IOPIN_PORTA
+#define FPGA_MEZZ_PROG_PIN 0 /* PA0 */
+#define FPGA_MEZZ_INIT_PORT IOPIN_PORTA
+#define FPGA_MEZZ_INIT_PIN 1 /* PA1 */
+#define FPGA_MEZZ_DONE_PORT IOPIN_PORTA
+#define FPGA_MEZZ_DONE_PIN 2 /* PA2 */
+#define FPGA_MEZZ_ENABLE_PORT IOPIN_PORTA
+#define FPGA_MEZZ_ENABLE_PIN 3 /* PA3 */
+
/*
* Internal Definitions
*
#ifdef CONFIG_MPC8260
+#define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */
+
/* This structure keeps track of the bd and buffer space usage. */
typedef struct i2c_state {
int rx_idx, tx_idx; /* index to next free rx/tx bd */
extern char NetOurRootPath[32]; /* Our root path */
extern ushort NetBootFileSize; /* Our boot file size in blocks */
/** END OF BOOTP EXTENTIONS **/
+extern ulong NetBootFileXferSize; /* size of bootfile in bytes */
extern uchar NetOurEther[6]; /* Our ethernet address */
extern uchar NetServerEther[6]; /* Boot server enet address */
extern IPaddr_t NetOurIP; /* Our IP addr (0 = unknown) */
#ifdef CONFIG_4xx
#include <ppc4xx.h>
#endif
+#ifdef CONFIG_HYMOD
+#include <asm/hymod.h>
+#endif
#include <flash.h>
#include <image.h>
unsigned int bi_plb_busfreq; /* PLB Bus speed, in Hz */
unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */
unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */
+#endif
+#if defined(CONFIG_HYMOD)
+ hymod_conf_t bi_hymod_conf; /* hymod configuration information */
#endif
mon_fnc_t *bi_mon_fnc; /* Pointer to monitor functions */
} bd_t;
unsigned long env_addr; /* Address of Environment struct */
unsigned long env_valid; /* Checksum of Environment valid? */
unsigned long relocated; /* Relocat. offset when running in RAM */
+ unsigned long have_console; /* serial_init() was called */
mon_fnc_t bi_mon_fnc; /* Monitor functions */
#if defined(CFG_ALLOC_DPRAM) || defined(CONFIG_8260)
unsigned int dp_alloc_base;
void console_init_f(void); /* Before relocation; uses the serial stuff */
void console_init_r(ulong); /* After relocation; uses the console stuff */
int console_assign (int file, char *devname); /* Assign the console */
+int ctrlc (void);
/*
* STDIO based functions (can always be used)
char NetOurNISDomain[32]={0,}; /* Our NIS domain */
char NetOurHostName[32]={0,}; /* Our hostname */
char NetOurRootPath[32]={0,}; /* Our bootpath */
-ushort NetBootFileSize=0; /* Out bootfile size in blocks */
+ushort NetBootFileSize=0; /* Our bootfile size in blocks */
/** END OF BOOTP EXTENTIONS **/
+ulong NetBootFileXferSize; /* The actual transferred size of the bootfile (in bytes) */
uchar NetOurEther[6]; /* Our ethernet address */
uchar NetServerEther[6] = /* Boot server enet address */
{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
}
}
+ NetBootFileXferSize = 0;
/*
* Main packet reception loop. Loop receiving packets until
eth_rx();
/*
- * Check the keyboard for a Key. Quit if we get one.
+ * Abort if ctrl-c was pressed.
*/
- if (tstc()) {
- (void) getc();
+ if (ctrlc()) {
printf("\nAbort\n");
return 0;
}
goto restart;
case NETLOOP_SUCCESS:
+ if (NetBootFileXferSize > 0) {
+ char buf[10];
+ printf("Bytes transferred = %ld (%lx hex)\n",
+ NetBootFileXferSize,
+ NetBootFileXferSize);
+ sprintf(buf, "%lx", NetBootFileXferSize);
+ setenv("filesize", buf);
+ }
eth_halt();
return 1;
static __inline__ void
store_block (unsigned block, uchar * src, unsigned len)
{
- (void)memcpy((void *)(load_addr + block * 512), src, len);
+ ulong offset = block * 512, newsize = offset + len;
+ (void)memcpy((void *)(load_addr + offset), src, len);
+ if (NetBootFileXferSize < newsize)
+ NetBootFileXferSize = newsize;
}
static void TftpSend (void);
TftpLastBlock = TftpBlock;
NetSetTimeout (TIMEOUT * CFG_HZ, TftpTimeout);
- /* ImageSize += len; */
store_block (TftpBlock - 1, pkt + 2, len);
/*
projects / users / rw / ppcboot.git / commitdiff