drm/amd/display: Ensure DMCUB idle before reset on DCN31/DCN35

[Why]
If we soft reset before halt finishes and there are outstanding
memory transactions then the memory interface may produce unexpected
results, such as out of order transactions when the firmware next runs.

These can manifest as random or unexpected load/store violations.

[How]
Increase the timeout before soft reset to ensure the DMCUB has quiesced.
This is effectively 1s maximum based on experimentation.

Use the enable bit check on DCN31 like we're doing on DCN35 and reorder
the reset writes to follow the HW programming guide.

Ensure we're reading SCRATCH7 instead of SCRATCH8 for the HALT code.
No current versions of DMCUB firmware use the SCRATCH8 boot bit to
dynamically switch where the HALT code goes to maintain backwards
compatibility with PSP.

Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Wayne Lin <wayne.lin@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
index 3d0bba602b53a7e308b9d3bfc26628ce200b232a..9796077885c942b63cb15d45a102fe001833556f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
@@ -83,8 +83,8 @@ static inline void dmub_dcn31_translate_addr(const union dmub_addr *addr_in,
 void dmub_dcn31_reset(struct dmub_srv *dmub)
 {
        union dmub_gpint_data_register cmd;
-       const uint32_t timeout = 100;
-       uint32_t in_reset, scratch, i, pwait_mode;
+       const uint32_t timeout = 100000;
+       uint32_t in_reset, is_enabled, scratch, i, pwait_mode;
 
        REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &in_reset);
 
@@ -108,7 +108,7 @@ void dmub_dcn31_reset(struct dmub_srv *dmub)
                }
 
                for (i = 0; i < timeout; ++i) {
-                       scratch = dmub->hw_funcs.get_gpint_response(dmub);
+                       scratch = REG_READ(DMCUB_SCRATCH7);
                        if (scratch == DMUB_GPINT__STOP_FW_RESPONSE)
                                break;
 
@@ -125,9 +125,14 @@ void dmub_dcn31_reset(struct dmub_srv *dmub)
                /* Force reset in case we timed out, DMCUB is likely hung. */
        }
 
-       REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 1);
-       REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);
-       REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1);
+       REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_enabled);
+
+       if (is_enabled) {
+               REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 1);
+               REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1);
+               REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);
+       }
+
        REG_WRITE(DMCUB_INBOX1_RPTR, 0);
        REG_WRITE(DMCUB_INBOX1_WPTR, 0);
        REG_WRITE(DMCUB_OUTBOX1_RPTR, 0);

diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
index e5e77bd3c31ea1b569d9d8574c0f9f49ef44a731..01d013a12b9476ef1aac7ef5d534a6ea6a87f20d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
@@ -88,7 +88,7 @@ static inline void dmub_dcn35_translate_addr(const union dmub_addr *addr_in,
 void dmub_dcn35_reset(struct dmub_srv *dmub)
 {
        union dmub_gpint_data_register cmd;
-       const uint32_t timeout = 100;
+       const uint32_t timeout = 100000;
        uint32_t in_reset, is_enabled, scratch, i, pwait_mode;
 
        REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &in_reset);
@@ -113,7 +113,7 @@ void dmub_dcn35_reset(struct dmub_srv *dmub)
                }
 
                for (i = 0; i < timeout; ++i) {
-                       scratch = dmub->hw_funcs.get_gpint_response(dmub);
+                       scratch = REG_READ(DMCUB_SCRATCH7);
                        if (scratch == DMUB_GPINT__STOP_FW_RESPONSE)
                                break;